Re: [Gems-users] Extending Ruby

["Dave Z." <zhu_dave@xxxxxxxxx>]

--- Greg Byrd <gbyrd@xxxxxxxx> wrote:


> I'm not totally confident in this answer, but I
> believe that the data is 
> actually read from memory by Simics.  When Ruby (the
> timing model) tells 
> Simics that the load is complete, the value that is
> stored in the 
> physical memory object is retrieved by the Simics
> processor model.  In 
> other words, data doesn't get moved around by Ruby. 
> 
> The directory controller is used when it receives a
> message from a 
> cache.  Ruby is event-driven -- the cache controller
> sends a message to 
> the directory in response to a cache miss; when that
> message arrives at 
> the directory, it triggers an event that is handled
> by the controller.

I'm not sure if the original AMD Opteron coherence
protocol has a directory controller. If that is the
case, could you please explain why you needed to
implement it?

> > Finally, is it possible to make data transfers
> between
> > processors? Is there something like
> > processor0.L2cacheMemory[address] =
> > processor1.L2cacheMemory[address]? How can I
> obtain
> > the machine id's of other processors in the
> system?
> >
> >   
> First, there's no data kept in the caches.  

I'm not sure if I understand clearly what you mean by
"there's no data kept in the caches". The data is
modeled to be loaded into given addresses in the
caches, or stored from the caches, right?

Thank you for your help and patience.

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