Re: [Gems-users] Extending Ruby


Date: Mon, 18 Sep 2006 14:15:23 -0500 (CDT)
From: Mike Marty <mikem@xxxxxxxxxxx>
Subject: Re: [Gems-users] Extending Ruby
> > I'm not totally confident in this answer, but I
> > believe that the data is
> > actually read from memory by Simics.  When Ruby (the
> > timing model) tells
> > Simics that the load is complete, the value that is
> > stored in the
> > physical memory object is retrieved by the Simics
> > processor model.  In
> > other words, data doesn't get moved around by Ruby.
> >
> > The directory controller is used when it receives a
> > message from a
> > cache.  Ruby is event-driven -- the cache controller
> > sends a message to
> > the directory in response to a cache miss; when that
> > message arrives at
> > the directory, it triggers an event that is handled
> > by the controller.
>
> I'm not sure if the original AMD Opteron coherence
> protocol has a directory controller. If that is the
> case, could you please explain why you needed to
> implement it?
>

In Ruby, we call the directory and memory controllers the same thing.
Yes, there is no per-block sharing state in the Opteron system.  However
MOESI_SMP_hammer does add some bits to each block to avoid the duplicate
data response that the actual Opteron's incur on any sharing miss.

If you want to model an exact Intel/AMD/etc system, you will need to make
changes yourself.

> > > Finally, is it possible to make data transfers
> > between
> > > processors? Is there something like
> > > processor0.L2cacheMemory[address] =
> > > processor1.L2cacheMemory[address]? How can I
> > obtain
> > > the machine id's of other processors in the
> > system?
> > >
> > >
> > First, there's no data kept in the caches.
>
> I'm not sure if I understand clearly what you mean by
> "there's no data kept in the caches". The data is
> modeled to be loaded into given addresses in the
> caches, or stored from the caches, right?
>

Ruby is a _timing model_.  It does not keep track of the actual data that
Simics uses.  It tells Simics how long to stall for a given memory
reference.

To make "data transfers" between processors, Ruby models how long it takes
to obtain coherence permission and transfer data.  It does this by sending
messages.

--Mike
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