Re: [Gems-users] Help in DirRequestFromL2Cache -> requestToDir

["Mike Marty" <mike.marty@xxxxxxxxx>]

A TBE is basically a MSHR (miss status handling register).  It keeps track of outstanding requests.  An L2->Memory prefetch shouldn't invovle the L1.

--Mike

On Dec 10, 2007 9:36 AM, Tushar Krishna ( tkrishna@xxxxxxxxxxxxx) <tkrishna@xxxxxxxxxxxxx> wrote:

Hi Mike,
I was initiating a prefetch inside the L2Cache_Controller in the a_issueGETS and b_issueGETX functions. But would it be better to initiate it from L2 Cache Wakeup itself so that the L2 Cache Transitions are not skipped?

Secondly, I wanted to know more about the role if the TBE. Is the role of the TBE to keep a copy of whichever request is sent to the directory from L2 and then remove it when the request completes?
Hence just before call back to L1, if I can check if that address in the TBE is a prefetch one, I can stop the call to L1.

Thanks
Tushar

----- Original Message -----
From: Mike Marty <mike.marty@xxxxxxxxx>
Date: Sunday, December 9, 2007 9:08 pm
Subject: Re: [Gems-users] Help in DirRequestFromL2Cache -> requestToDir
To: Gems Users <gems-users@xxxxxxxxxxx>

> On Dec 9, 2007 2:06 AM, Tushar Krishna ( tkrishna@xxxxxxxxxxxxx) <
> tkrishna@xxxxxxxxxxxxx> wrote:
>
> > Hi,
> >
> > I am trying to track the memory request as it goes from L2 to the
> > Memory/Directory and back as I'm trying to implement a prefetch
> unit at L2.
> > When the cache line request message is sent from the L2 Cache to the
> > Memory/Directory, I see that it is enquued in the
> > m_L2Cache_DirRequestFromL2Cache_vec buffer.
> >
> > But the Directory_Wakeup looks at the
> m_Directory_requestToDir_vec buffer.
> >
> > Where does the transfer from m_L2Cache_DirRequestFromL2Cache_vec to
> > m_Directory_requestToDir_vec buffer take place?
> > Similarly when the addr is sent back.
> >
>
> Through the Ruby interconnection network.
>
>
> > Can the entire address traversal be tracked?
> >
>
> You can enable debugging flags in the network if you want, but this is
> really fine-grained detail.
>
>
> > I modified the Address class to have a private member
> prefetch_bit so that
> > as the address moves on, its status as a prefetch address or a
> normal miss
> > stays with it so that when it returns back to L2, I can stop the
> call back
> > to L1...
> >
>
> I would perhaps add a Prefetch bit to the RequestMsg.
>
>
> > Am I trying something too elaborate here for the prefetch?
> > I am using the MSI_MOSI_CMP_bcast protocol which requires
> inclusion. So
> > would an extra request (for prefetch) not being allowed to go
> back to L1
> > create problems?
> >
>
> You should be able to initiate an L2->Memory prefetch without the L1's
> knowledge.
>
> --Mike
>

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