Yup, I wrote my own workload. Its really simple, I'm just incrementing
a global variable. It looks like:
-------------------------
for(i = 0 ; i < num_ops ; ++i)
{
BEGIN_TRANSACTION(0)
temp = counter;
temp = temp + 1;
counter = temp;
COMMIT_TRANSACTION(0)
}
------------------------
counter is global variable and temp is local.
I'm attaching the ruby parameter list.
Shakeel
On Fri, Mar 20, 2009 at 11:12 PM, Polina Dudnik <pdudnik@xxxxxxxxx> wrote:
> Did you make your own transactional workload? If so, what do you have inside
> the transaction?
>
> Also, did you change any of the ruby parameters?
>
> On Fri, Mar 20, 2009 at 5:28 PM, Shakeel Butt <shakeel.butt@xxxxxxxxx>
> wrote:
>>
>> Hi,
>>
>> I am having problem with simics memory accesses during transactional
>> workload. The physical address generated by simics are larger than the
>> actual memory presented in the system. In "SimicsDriver::makeRequest"
>> all the such accesses are ignored by ruby. So, the memory accesses
>> during transactions are ignored. I am running 8 cpu system with
>> (256*8) MB of RAM but the physical addresses generated are like 40
>> bits. I have checked the logical address and that address is correct
>> (same as in program). Am I missing something?
>>
>> One more thing has anyone tried Tourmaline on simics 3.0 or tried to
>> migrate it to simics 3.0?
>>
>> Shakeel
>> _______________________________________________
>> Gems-users mailing list
>> Gems-users@xxxxxxxxxxx
>> https://lists.cs.wisc.edu/mailman/listinfo/gems-users
>> Use Google to search the GEMS Users mailing list by adding
>> "site:https://lists.cs.wisc.edu/archive/gems-users/"; to your search.
>>
>
>
> _______________________________________________
> Gems-users mailing list
> Gems-users@xxxxxxxxxxx
> https://lists.cs.wisc.edu/mailman/listinfo/gems-users
> Use Google to search the GEMS Users mailing list by adding
> "site:https://lists.cs.wisc.edu/archive/gems-users/"; to your search.
>
>
>
g_RANDOM_SEED : 1
g_DEADLOCK_THRESHOLD : 500000
RANDOMIZATION : false
g_SYNTHETIC_DRIVER : false
g_DETERMINISTIC_DRIVER : false
g_FILTERING_ENABLED : false
g_DISTRIBUTED_PERSISTENT_ENABLED : true
g_DYNAMIC_TIMEOUT_ENABLED : true
g_RETRY_THRESHOLD : 1
g_FIXED_TIMEOUT_LATENCY : 300
g_trace_warmup_length : 1000000
g_bash_bandwidth_adaptive_threshold : 0.750000
g_tester_length : 0
g_synthetic_locks : 2048
g_deterministic_addrs : 1
g_SpecifiedGenerator : DetermInvGenerator
g_callback_counter : 0
g_NUM_COMPLETIONS_BEFORE_PASS : 0
g_NUM_SMT_THREADS : 1
g_think_time : 5
g_hold_time : 5
g_wait_time : 5
PROTOCOL_DEBUG_TRACE : true
DEBUG_FILTER_STRING : none
DEBUG_VERBOSITY_STRING : none
DEBUG_START_TIME : 0
DEBUG_OUTPUT_FILENAME : none
SIMICS_RUBY_MULTIPLIER : 4
OPAL_RUBY_MULTIPLIER : 1
TRANSACTION_TRACE_ENABLED : false
USER_MODE_DATA_ONLY : false
PROFILE_HOT_LINES : false
PROFILE_ALL_INSTRUCTIONS : false
PRINT_INSTRUCTION_TRACE : false
g_DEBUG_CYCLE : 0
BLOCK_STC : false
PERFECT_MEMORY_SYSTEM : false
PERFECT_MEMORY_SYSTEM_LATENCY : 0
DATA_BLOCK : false
REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH : true
g_SIMICS : true
L1_CACHE_ASSOC : 4
L1_CACHE_NUM_SETS_BITS : 8
L2_CACHE_ASSOC : 4
L2_CACHE_NUM_SETS_BITS : 13
g_MEMORY_SIZE_BYTES : 2147483648
g_DATA_BLOCK_BYTES : 64
g_PAGE_SIZE_BYTES : 4096
g_REPLACEMENT_POLICY : PSEDUO_LRU
g_NUM_PROCESSORS : 8
g_NUM_L2_BANKS : 8
g_NUM_MEMORIES : 8
g_PROCS_PER_CHIP : 8
g_NUM_CHIPS : 1
g_NUM_CHIP_BITS : 0
g_MEMORY_SIZE_BITS : 31
g_DATA_BLOCK_BITS : 6
g_PAGE_SIZE_BITS : 12
g_NUM_PROCESSORS_BITS : 3
g_PROCS_PER_CHIP_BITS : 3
g_NUM_L2_BANKS_BITS : 3
g_NUM_L2_BANKS_PER_CHIP_BITS : 3
g_NUM_L2_BANKS_PER_CHIP : 8
g_NUM_MEMORIES_BITS : 3
g_NUM_MEMORIES_PER_CHIP : 8
g_MEMORY_MODULE_BITS : 22
g_MEMORY_MODULE_BLOCKS : 4194304
MAP_L2BANKS_TO_LOWEST_BITS : false
DIRECTORY_CACHE_LATENCY : 6
NULL_LATENCY : 1
ISSUE_LATENCY : 2
CACHE_RESPONSE_LATENCY : 12
L2_RESPONSE_LATENCY : 6
L2_TAG_LATENCY : 6
L1_RESPONSE_LATENCY : 3
MEMORY_RESPONSE_LATENCY_MINUS_2 : 158
DIRECTORY_LATENCY : 80
NETWORK_LINK_LATENCY : 1
COPY_HEAD_LATENCY : 4
ON_CHIP_LINK_LATENCY : 1
RECYCLE_LATENCY : 10
L2_RECYCLE_LATENCY : 5
TIMER_LATENCY : 10000
TBE_RESPONSE_LATENCY : 1
PERIODIC_TIMER_WAKEUPS : true
PROFILE_EXCEPTIONS : false
PROFILE_XACT : true
PROFILE_NONXACT : false
XACT_DEBUG : true
XACT_DEBUG_LEVEL : 3
XACT_MEMORY : true
XACT_ENABLE_TOURMALINE : true
XACT_NUM_CURRENT : 0
XACT_LAST_UPDATE : 0
XACT_ISOLATION_CHECK : false
PERFECT_FILTER : true
READ_WRITE_FILTER : Perfect_
PERFECT_VIRTUAL_FILTER : true
VIRTUAL_READ_WRITE_FILTER : Perfect_
PERFECT_SUMMARY_FILTER : true
SUMMARY_READ_WRITE_FILTER : Perfect_
XACT_EAGER_CD : true
XACT_LAZY_VM : false
XACT_CONFLICT_RES : BASE
XACT_VISUALIZER : false
XACT_COMMIT_TOKEN_LATENCY : 0
XACT_NO_BACKOFF : false
XACT_LOG_BUFFER_SIZE : 0
XACT_STORE_PREDICTOR_HISTORY : 256
XACT_STORE_PREDICTOR_ENTRIES : 256
XACT_STORE_PREDICTOR_THRESHOLD : 4
XACT_FIRST_ACCESS_COST : 0
XACT_FIRST_PAGE_ACCESS_COST : 0
ENABLE_MAGIC_WAITING : false
ENABLE_WATCHPOINT : false
XACT_ENABLE_VIRTUALIZATION_LOGTM_SE : false
ATMTP_ENABLED : false
ATMTP_ABORT_ON_NON_XACT_INST : false
ATMTP_ALLOW_SAVE_RESTORE_IN_XACT : false
ATMTP_XACT_MAX_STORES : 32
ATMTP_DEBUG_LEVEL : 0
L1_REQUEST_LATENCY : 2
L2_REQUEST_LATENCY : 4
SINGLE_ACCESS_L2_BANKS : true
SEQUENCER_TO_CONTROLLER_LATENCY : 4
L1CACHE_TRANSITIONS_PER_RUBY_CYCLE : 32
L2CACHE_TRANSITIONS_PER_RUBY_CYCLE : 32
DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE : 32
g_SEQUENCER_OUTSTANDING_REQUESTS : 16
NUMBER_OF_TBES : 128
NUMBER_OF_L1_TBES : 32
NUMBER_OF_L2_TBES : 32
FINITE_BUFFERING : false
FINITE_BUFFER_SIZE : 3
PROCESSOR_BUFFER_SIZE : 10
PROTOCOL_BUFFER_SIZE : 32
TSO : false
g_NETWORK_TOPOLOGY : PT_TO_PT
g_CACHE_DESIGN : NUCA
g_endpoint_bandwidth : 10000
g_adaptive_routing : true
NUMBER_OF_VIRTUAL_NETWORKS : 6
FAN_OUT_DEGREE : 4
g_PRINT_TOPOLOGY : true
XACT_LENGTH : 0
XACT_SIZE : 0
ABORT_RETRY_TIME : 0
g_GARNET_NETWORK : false
g_DETAIL_NETWORK : false
g_NETWORK_TESTING : false
g_FLIT_SIZE : 16
g_NUM_PIPE_STAGES : 4
g_VCS_PER_CLASS : 4
g_BUFFER_SIZE : 4
MEM_BUS_CYCLE_MULTIPLIER : 10
BANKS_PER_RANK : 8
RANKS_PER_DIMM : 2
DIMMS_PER_CHANNEL : 2
BANK_BIT_0 : 8
RANK_BIT_0 : 11
DIMM_BIT_0 : 12
BANK_QUEUE_SIZE : 12
BANK_BUSY_TIME : 11
RANK_RANK_DELAY : 1
READ_WRITE_DELAY : 2
BASIC_BUS_BUSY_TIME : 2
MEM_CTL_LATENCY : 12
REFRESH_PERIOD : 1560
TFAW : 0
MEM_RANDOM_ARBITRATE : 0
MEM_FIXED_DELAY : 0
|
![[Computer Systems Lab]](https://www-auth.cs.wisc.edu/pics/csl_logo.gif){kind=logo}