Re: [Gems-users] How to collect multicore coherence traffic

[aparnam@xxxxxxxxxxxxxxxxx]

Hi,
Directly adding in SLICC code is difficult. But if you can add in file in
ruby/generated/MOESI... directory which gets created on compiling ruby.
check L2 and L1 controllers files for more info.
thanks,
Aparna

> Hi All,
>
>     I am a newbie to GEMS. Now, I want to utilize GEMS framework to
> collect the cache coherence traffic of real applications running on a
> multicore platform. Imagine that I use the directory coherence
> protocol for a 16-core CMP with private L1 cache and shared L2 cache
> (NUCA-like). How can I collect the various on-chip traffic, such as
> the L2 read, L2 write and L1 invalidate, etc.
>     Where can I add codes in the GEMS to implement such function? In SLICC
> or somewhere?
>
>     Thanks in advance.
>
> Regards,
> Jianhua
>
>
>
>
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