This is the 1st September 2007 Digest of SIGARCH Messages (sigarch-sep07a):
* SIGARCH Distinguished Service Award
http://www.sigarch.org/dsa/dsa.html
Submittted by Doug Burger <dburger@xxxxxxxxxxxxx>
* dasCMP 2007 Call for Papers: Workshop on Design, Architecture and
Simulation of Chip Multi-Processors
http://www.crhc.uiuc.edu/~rakeshk/dasCMP
Submitted by Rakesh Kumar <rakeshk@xxxxxxxx>
* ISPASS 2008 Call for Papers: International Symposium on Performance Analysis of
Systems and Software ? ISPASS-2008
http://ispass.org/ispass2008/
Submitted by Ould-ahmed-vall, Elmoustapha <elmoustapha.ould-ahmed-vall@xxxxxxxxx>
* RAAW-2 Call for Papers: SECOND ANNUAL RECONFIGURABLE AND ADAPTIVE ARCHITECTURE
WORKSHOP (RAAW-2)
http://www.comparch.binghamton.edu/raaw/
Submitted by Mohamed Zahran <mzahran@xxxxxxxxxxxxx>
* HPCA Call for Workshops and Tutorials: 14th International Symposium on
High-Performance Computer Architecture
http://www.cs.utah.edu/hpca08/
Submitted by Liqun Cheng <legion@xxxxxxxxxxx>
* SMART'08 Call for Papers: 2nd Workshop on Statistical and Machine learning approaches
to ARchitecture and compilaTion
http://www.hipeac.net/smart-workshop.html
Submitted by Grigori Fursin <grigori.fursin@xxxxxxxx>
* Computer Architecture Letters New Papers online
http://www.comp-arch-letters.org
Submitted by Kevin Skadron <skadron@xxxxxxxxxxxxxxx>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@xxxxxxx
* Archive: http://lists.cs.wisc.edu/archive/sigarch-members/
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@xxxxxxx with message body: unsubscribe SIGARCH-MEMBERS
-----------------------------------------------------------------
Doug Burger Office: 3.432 ACES
Associate Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
The University of Texas at Austin Fax: 512-232-1413
1 University Station, #C0500 E-mail: dburger@xxxxxxxxxxxxx
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
----------------------------------------------------------------------
----------------------------------------------------------------------
* SIGARCH Distinguished Service Award
The ACM SIGARCH Distinguished Service Award
This annual award is presented to an individual who has contributed important service
to the computer architecture community.
Recipients receive a memento engraved with their name along with a $1000 honorarium.
The award is presented by the SIGARCH chair at ISCA during ISCA's award presentation
session. The award recipient also receives up to $2000 towards support for travel costs,
including airfare, hotel, and conference registration for ISCA. The recipient is listed
with a citation for their award on a SIGARCH Distinguished Service Award web page.
The selection committee consists of 3 or more members and is appointed by the SIGARCH
chair. The committee typically includes recent recipients of the award and current
SIGARCH executive committee members. The committee solicits nominations from the
computer architecture community in a variety of ways including announcements in SIGARCH's
newsletter and postings on appropriate newsgroups and websites. The committee considers
all external nominations, plus any internal nominations from members of the committee,
in the context of the nominees' specific and general service contributions to the
computer architecture community.
Nominations
Nominations can be submitted at any time to the secretary/treasurer of SIGARCH.
Nominations submitted by February 15th will be considered for that year's award.
A nomination for the distinguished service award that is not awarded will remain valid
for 3 years.
Each nomination should consist of the following items:
* Name, address, phone number, and email address of the person making the nomination
(the nominator).
* Name, address, phone number, and email address of the candidate for whom an award
is recommended (the nominee).
* A short statement (200-500 words) explaining why the nominee deserves the award in
question.
* Names and email addresses of 4-7 people who the nominator believes will support
the nomination.
* The awards committee will ask some of these people for their opinions.
The committee will not consider self-nominations.
----------------------------------------------------------------------
----------------------------------------------------------------------
* dasCMP 2007 Call for Papers: Workshop on Design, Architecture and
Simulation of Chip Multi-Processors
Call for Papers
Workshop on Design, Architecture and Simulation of Chip Multi-Processors
dasCMP 2007
http://www.crhc.uiuc.edu/~rakeshk/dasCMP
Held in conjunction with the 40th Annual International Symposium on Microarchitecture
Sunday, December 2, 2007, Chicago
Organizers
Norman P. Jouppi, HP Labs (norm.jouppi@xxxxxx)
Rakesh Kumar, UIUC (rakeshk@xxxxxxxx)
Dean M. Tullsen, UC San Diego (tullsen@xxxxxxxxxxx)
Goal of the Workshop
Chip multiprocessor architectures are becoming increasingly attractive as an option
to provide high instruction throughput while keeping power and complexity under control.
Such architectures have also been shown to have scalability and productivity advantages.
Multi-core processors are fast becoming mainstream.
However, putting multiple cores on a die throws open several interesting research and
design issues. From choosing the number of cores on the die to choosing the complexity
of these cores, from constructing a chip multiprocessor out of off-the-shelf cores to
creating a customized ``multi-core aware'' multi-core design, there are several difficult
questions that need to be addressed. Connecting the cores, determining the right memory
subsystem, ensuring coherence and consistency of data, and trying to limit the area and
power budgets, all require a deep understanding of issues and innovative application of
ideas. Even simulating and evaluating a chip multiprocessor represents a significant
challenge. There are equally interesting issues regarding programming and compilation
for chip multiprocessors. All these questions and issues become more difficult and
complicated for architectures with more than two cores.
The goal of this workshop is to bring together researchers, computer architects, and
engineers working on a broad spectrum of topics pertaining to the architecture, simulation,
and design of chip multiprocessors. The workshop will provide a forum for presenting and
exchanging new ideas and experiences in this area and to discuss and explore hardware/
software techniques and tools for efficient multi-core computation.
Contributions from all aspects of multi-core architecture, design and simulation are
encouraged; related areas like application of CMPs to solve new problems and programming
and compilation for CMP architectures are welcome as well.
Topics of Interest
The topics of interest for the workshop will include but are not limited to:
*Core design for CMPs, e.g. helper cores, conjoined-cores, heterogeneous multi-core
architectures, etc.
*Novel Microarchitectures, e.g. tiled architectures, master-slave architectures, etc.
*Interconnects in CMPs, e.g. connections between cores, connections between cores and
on-chip memory, networks-on-chip, etc.
*Cache coherence and consistency for CMPs
*On-chip/off-chip memory hierarchy and design for CMPs
*Applications of CMP architectures for solving problems, e.g. using multiple cores to
enhance security, reliability, improve single-thread performance, reduce power, etc.
*Speculative Multithreading for CMPs
*Compiler, scheduling, and OS support for CMPs
*Programmability enhancements for CMPs
*Simulation and evaluation of CMPs, e.g. new simulators, simulation techniques,
analytical evaluations
*Efficient design space exploration for multi-core architectures
*Workload/benchmark design and analysis for multi-core processors
*Performance evaluation/analysis/design of real multi-core processors
Full length conference papers are fine but not a requirement. Out-of-the box idea/
position papers specially encouraged.
Program Committee (Incomplete List)
Michael Gschwind, IBM
Norman P. Jouppi, HP
Stephen Keckler, UT Austin
Rakesh Kumar, UIUC
Jim Laudon, Sun
Kunle Olukotun, Stanford
Mark Oskin, UWash
Li-Shiuan Peh, Princeton
Ronny Ronen, Intel
Per Stenstrom, Chalmers
Dean Tullsen, UCSD
Schedule
Submission Deadline: September 10, 2007 (one week extension upon request)
Acceptance Notification: November 6, 2007
Final Version due: November 18, 2007
For Questions, please email rakeshk@xxxxxxxx
----------------------------------------------------------------------
----------------------------------------------------------------------
* ISPASS 2008 Call for Papers: International Symposium on Performance Analysis of
Systems and Software ? ISPASS-2008
CALL FOR PAPERS:
International Symposium on Performance Analysis of Systems and Software ? ISPASS-2008
================
April 2-4, 2008
Austin, Texas
===============
Sponsored by the IEEE Computer Society?s TCI, TCCA, and TC-uARCH
===============================================================================
The IEEE International Symposium on Performance Analysis of Systems and Software provides
a forum for sharing advanced academic and industrial research work focused on performance
analysis in the design of computer systems and software. Authors are invited to submit
previously unpublished work for possible presentation at this conference. Papers are
solicited in fields that include the following:
- Benchmarking
- Workload characterization
- Simulation
- Analytical models
- Statistical approaches
- Performance metrics
- Microprocessor, memory, and disk performance issues
- Multi-core, multithreaded, and multiprocessor performance issues
- Performance of computer networks
- Performance analysis of software
- Performance of data-intensive applications
- Tuning of application code
- Tuning of system code
- Tracing, profiling, and simulation tools
- Bottleneck identification
- Power and thermal modeling
- Performance validation
- Characterization of emerging applications
- Case studies
- Confirmations or refutations of important prior results
Papers of no more than 22 double-spaced pages (no less than 11pt font), including figures,
are solicited. Authors are requested to submit papers in PDF format. More information will
be available on the ISPASS website (http://ispass.org) as the submission deadline approaches.
==========================================================================================
COMMITTEES
==========
GENERAL CHAIR:
Sandhya Dwarkadas, University of Rochester
(sandhya@xxxxxxxxxxxxxxxx)
PROGRAM CHAIR:
Dean Tullsen, UC San Diego
(tullsen@xxxxxxxxxxx)
PROGRAM COMMITTEE:
Michael Adler, Intel
David Brooks, Harvard University
David Christie, AMD
Jamison Collins, Intel
Lieven Eeckhout, Ghent University
Babak Falsafi, CMU
Paolo Faraboschi, HP
Annie Foong, Intel
Mike Gschwind, IBM
Rajiv Gupta, UC Riverside
Sudhanva Gurumurthi, University of Virginia
Ravi Iyer, Intel
Rakesh Kumar, UIUC
Mikko Lipasti, Univ. of Wisconsin
Gabriel Loh, Georgia Tech
Geoff Lowney, Intel
Vijay Pai, Purdue University
Scott Rixner, Rice University
Yiannakis Sazeides, University of Cyprus
Tim Sherwood, UCSB
Jim Smith, University of Wisconsin
Mark Squillante, IBM
Pen-Chung Yew, University of Minnesota
LOCAL ARRANGEMENT CHAIRS:
Nasr Ullah, Freescale
PUBLICITY CHAIR:
Elmoustapha Ould-Ahmed-Vall, Intel
FINANCE CHAIR:
Nadeem Malik, IBM
WEB CHAIR:
Byeong Kil Lee, Texas Instruments
SUBMISSION AND REVIEW WEB CHAIR:
Leo Porter, UCSD
PUBLICATION CHAIR
Russ Joseph, Northwestern University
WORKSHOPS/TUTORIALS CHAIR:
Tao Li, University of Florida
REGISTRATION CHAIR:
Rajeev Balasubramonian, University of Utah
==========================================================================================
Important Dates
===============
Abstract due: September 21, 2007
Full submission due: September 28, 2007 (no extensions)
Notification of acceptance: December 17, 2007
Final version due: January 25, 2008
==========================================================================================
For more information, visit the ISPASS web site at http://ispass.org
----------------------------------------------------------------------
----------------------------------------------------------------------
* RAAW-2 Call for Papers: SECOND ANNUAL RECONFIGURABLE AND ADAPTIVE ARCHITECTURE
WORKSHOP (RAAW-2)
SECOND ANNUAL RECONFIGURABLE AND ADAPTIVE ARCHITECTURE WORKSHOP (RAAW-2)
http://www.comparch.binghamton.edu/raaw/
To be held in conjunction with the
The 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2007
Chicago, Illinois, USA
Workshop Theme
--------------
The tremendous advances in process technology provide architects and
microarchitects with many interesting opportunities for making use of
the huge transistor budget to enhance performance and increase
throughput. However, the complexity of software applications and
system software presents a challenging problem. The varying
requirements of the different applications running on a single
machine, as well as the changing behavior of a single application
during its lifetime, make choosing a suitable general purpose
architecture a big challenge. This raises the need for an architecture
that can adapt to the different requirements of the applications.The
power consumption limits and the growing importance of reliability
further add to the appeal of such
adaptive architectures.
The Reconfigurable and Adaptive Architecture Workshop provides a
high-quality forum for
computer scientists and engineers to present their latest research
findings in the rapidly
evolving field of reconfigurable and adaptive architectures.
Submission Topics
-----------------
Topics of interest include, but are not limited to:
* High performance adaptive and reconfigurable architectures
* Power-Aware and Thermal-Aware architectures
* Adaptive architectures for enhanced hardware reliability
* Compilation techniques for adaptive and reconfigurable architectures
* Dynamic compilation and runtime execution environments
* Heterogeneous multiprocessing on a chip
* Reconfigurable interconnection
* Hardware/software trade-offs
* Novel architectures and micro-architectures
* Reconfigurable embedded computing systems
* Memory management techniques
* Static and dynamic profiling techniques
* Program phase detection and exploitation techniques
* Hardware acceleration through reconfiguration
* Integration of FPGAs with microprocessors
Submission Guidelines
---------------------
The Program Committee invites authors to submit papers up to 5000
words in length,
describing original, unpublished recent work related to the workshop theme.
Submission must be in pdf format and emailed to raaw@xxxxxxxxxxxxxxx
The submission should include the contact person's email address on
the front page.
The selected papers will be considered for publication in a special
theme issue of JILP.
At least one of the author(s) of an accepted paper is expected to
register for the workshop
and present the paper.
Important Deadlines
-------------------
Paper Submission: September 18, 2007
Acceptance Notification: October 26, 2007
Final version of papers: November 12, 2007
Organizers
-----------
Aneesh Aggarwal
Electrical and Computer Engineering
SUNY Binghamton
Pradip Bose
IBM T. J. Watson Research Center
Mohamed Zahran
Electrical Engineering
City University of New York
Program Committee
----------------------------
Bryan Black (AMD)
Alper Buyuktosunoglu (IBM)
Joel Emer (Intel)
Onur Mutlu (Microsoft)
Eric Rotenberg (NCSU)
Rajiv Gupta (UCR)
Scott Mahlke (UMich)
Amir Roth (UPenn)
Contact Us at raaw@xxxxxxxxxxxxxx
----------------------------------------------------------------------
----------------------------------------------------------------------
* HPCA Call for Workshops and Tutorials: 14th International Symposium on
High-Performance Computer Architecture
HPCA-08 Call for Workshop and Tutorial Proposals
14th International Symposium on High-Performance Computer Architecture
Salt Lake City, Feb. 16-20, 2008, (collocated with PPoPP '08)
http://www.cs.utah.edu/hpca08/
Deadline: September 24th, 2006
Send Workshop proposals to Mark Heinrich (heinrich@xxxxxxxxxxxx)
and Tutorial proposals to Jose Gonzalez (pepe.gonzalez@xxxxxxxxx)
We welcome proposals for workshops and tutorials related to computer
architecture. A complete list of topics of interest can be found in the HPCA-14
call for papers. See previous HPCAs (http://www.hpcaconf.org) for example
workshops and tutorials. Please submit your Workshop proposal (no more than 2
pages) to Mark Heinrich (heinrich@xxxxxxxxxxxx) and your tutorial proposal (no
more than 2 pages) to Jose Gonzalez (pepe.gonzalez@xxxxxxxxx) on or before
September 24th , 2007.
For workshops, please include in your proposal:
* title of the workshop
* organizers and their affiliations
* sample call for papers, including the workshop's main topics
* expected duration of the workshop; i.e., 1/2 day, full day, or 2 days
* if the workshop was previously held, the number of published papers and
attendees at the last workshop
For tutorials, include:
* title of the tutorial
* organizers, presenters, and their affiliations
* abstract of the tutorial
* a list of topics to be covered and some of their related bibliography
* expected duration of the tutorial; i.e., 1/2 day, full day, or 2 days
* if the tutorial was previously held, the location (i.e., which
conference), date, and number of attendees at the last tutorial
----------------------------------------------------------------------
----------------------------------------------------------------------
* SMART'08 Call for Papers: 2nd Workshop on Statistical and Machine learning approaches
to ARchitecture and compilaTion
Apologies if you receive multiple copies of this call.
********************************************************************************
CALL FOR PAPERS
2nd Workshop on
Statistical and Machine learning approaches
to ARchitecture and compilaTion
(SMART'08)
http://www.hipeac.net/smart-workshop.html
January 27, 2008, Goteborg, Sweden
(co-located with HiPEAC 2008 Conference)
********************************************************************************
The rapid rate of architectural change has placed enormous pressure on
compiler writers to keep pace with microprocessor evolution. This
problem is compounded by the current trend to have multi-cores and
multi-threading which makes such systems increasingly difficult to
target. Also, current methods of designing computer systems will no
longer be feasible in 10-15 years time; what is needed are new
innovative approaches to architecture design that scale both with
advances in underlying technology and with future application domains.
In recent years, several papers have been published showing great
potential in constructing compilers and architectures using approaches
such as machine learning and search.
The purpose of this workshop is to promote new ideas and to present
recent developments in compiler and architecture design using machine
learning, statistical approaches, and search in order to enhance their
performance, scalability, and adaptability.
Topics of interest include (but are not limited to):
Machine Learning, Statistical Approaches, or Search applied to
* Feedback-Directed Compilation
* Auto-tuning Programs + Language Extensions
* Library Generators
* Iterative Compilation
* Dynamic Compilation/Adaptive Execution
* Parallel Compiler Optimizations
* Low-power Optimizations
* Simulation
* Performance Models
* Adaptive Processor and System Architecture
* Design Space Exploration
* Other Topics relevant to Intelligent and Adaptive Compilers/Architectures
**** Paper Submission Guidelines ****
Paper length - maximum 15 pages.
Papers must be submitted in the PDF (preferably) or postscript
formats. Email your submissions to mob@xxxxxxxxxxxx or use
the workshop submission website.
Proceedings: An informal collection of the papers to be presented will
be distributed at the workshop. Questions regarding the workshop
proceedings should be forwarded to mob@xxxxxxxxxxxxx
All accepted papers will appear on the workshop website.
**** Important Dates ****
Deadline for submission: November 2, 2007
Decision notification: November 30, 2007
Workshop: January 27, 2008
Organizer
Michael O'Boyle, University of Edinburgh UK
Program Committee
Francois Bodin, IRISA, France
Calin Cascaval, IBM T.J. Watson Research Center, USA
John Cavazos, University of Delaware, USA
Lieven Eeckhout, Ghent University, Belgium
Ari Freund, IBM Haifa Research Lab, Israel
Grigori Fursin, INRIA Futurs, France
Michael O'Boyle, University of Edinburgh UK
David Padua, University of Illinois at Urbana-Champaign, USA
Devika Subramanian, Rice University, USA
Olivier Temam, INRIA Futurs, France
Matthew J. Thazhuthaveetil, Indian Institute of Science, India
Richard Vuduc, Georgia Institute of Technology, USA
David Whalley, Florida State University, USA
Chris Williams, University of Edinburgh, UK
----------------------------------------------------------------------
----------------------------------------------------------------------
* Computer Architecture Letters online
New papers published online by IEEE Computer Architecture Letters
Computer Architecture Letters announces our two most recent papers,
which are available now via IEEE Xplore. We happy to report that, as
recognition of Computer Architecture Letters has grown, the submission
rate has nearly doubled this year. We continue to seek new submissions
and remain committed to fast and accurate review. Our mean time to
decision in 2007 has been 23 days, with an acceptance rate of
approximately 24%. For more information on submission, please see
http://www.comp-arch-letters.org
- X. Xiao and J. Lee. "A Novel Parallel Deadlock Detection Algorithm and Hardware for
Multiprocessor System-on-a-Chip." Computer Architecture Letters, vol. 6, August 2007.
- D. August, J. Chang, S. Girbal, D. Gracia-Perez, G. Mouchard, O. Temam, and
N. Vachharajani. "UNISIM: An Open Simulation Environment and Library for Complex
Architecture Design and Collaborative Development."
Computer Architecture Letters, vol. 6, August 2007.
Abstracts
---------
- X. Xiao and J. Lee. "A Novel Parallel Deadlock Detection Algorithm and Hardware for
Multiprocessor System-on-a-Chip." Computer Architecture Letters, vol. 6, August 2007.
Abstract:
Given the projected dramatic increase in the number of processors and resources in a
system-on-a-chip, a quadratic increase in the likelihood of deadlock is predicted due
to complex system behavior. To deal with this issue, we here present a novel parallel
hardware-oriented deadlock detection algorithm with O(1) deadlock detection and
O(min(m,n)) preparation, where m and n are the numbers of processes and resources,
respectively. Our contributions are (i) the first O(1) deadlock detection hardware
implementation and (ii) a new algorithmic method of achieving O(min(m,n)) overall
run-time complexity. We implement our algorithm in Verilog HDL and demonstrate that
deadlock detection always takes only two clock cycles regardless of the size of a
system (i.e., m and n).
- D. August, J. Chang, S. Girbal, D. Gracia-Perez, G. Mouchard, O. Temam, and
N. Vachharajani. "UNISIM: An Open Simulation Environment and Library for Complex
Architecture Design and Collaborative Development."
Computer Architecture Letters, vol. 6, August 2007.
Abstract:
Simulator development is already a huge burden for many academic and industry research
groups; future complex or heterogeneous multi-cores, as well as the multiplicity of
performance metrics and required functionality, will make matters worse. We present
a new simulation environment, called UNISIM, which is designed to rationalize simulator
development by making it possible and efficient to distribute the overall effort over
multiple research groups, even without direct cooperation. UNISIM achieves this goal
with a combination of modular software development, distributed communication protocols,
multi-level abstract modeling, interoperability capabilities, a set of simulator services
APIs, and an open library/repository for providing a consistent set of simulator modules.
|
![[Computer Systems Lab]](https://www-auth.cs.wisc.edu/pics/csl_logo.gif){kind=logo}