This is the 2nd September 2007 Digest of SIGARCH Messages (sigarch-sep07b):
* NSF Computing Processes and Artifacts (CPA) Cluster Solicitation
http://nsf.gov/pubs/2007/nsf07587/nsf07587.htm
Submitted by Timothy M. Pinkston <tpink@xxxxxxx>
* NSF "Expeditions in Computing" (Expeditions) Solicitation
http://nsf.gov/pubs/2007/nsf07592/nsf07592.htm
Submitted by Timothy M. Pinkston <tpink@xxxxxxx>
* STAMP Release: Stanford Transactional Applications for Multi-Processing (STAMP)
http://stamp.stanford.edu
Submitted by Christos Kozyrakis <christos@xxxxxxxxxxxxxxx>
* IISWC 2007 Call for Participation: Tenth IEEE Intl Symposium on Workload Characterization
(IISWC 2007)
http://www.iiswc.org
Submitted by Bhuvan Urgaonkar <bhuvan@xxxxxxxxxxx>
* INA-OCMC Call for Papers: Interconnection Network Architectures: On-Chip, Multi-Chip
http://www.disca.upv.es/jflich/wina/wina.html
Submitted by Thomas Sodring <tsodring@xxxxxxxxx>
* Computing Frontiers 2008 Call for Papers: 2008 ACM International Conference on Computing
Frontiers
http://www.computingfrontiers.org/
Submitted by Julita Corbalan <juli@xxxxxxxxxx>
* ASPLOS-XIII Call for Workshops and Tutorials
http://research.microsoft.com/asplos08
Submitted by Michael Swift <swift@xxxxxxxxxxx>
* ACM - INFOSYS FOUNDATION AWARD
http://www.acm.org/news/featured/press-room/news-releases/infosys
Submitted by Rosemary McGuinness <mcguinness@xxxxxxxxxx>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@xxxxxxx
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Doug Burger Office: 3.432 ACES
Associate Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
The University of Texas at Austin Fax: 512-232-1413
1 University Station, #C0500 E-mail: dburger@xxxxxxxxxxxxx
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* NSF Computing Processes and Artifacts (CPA) Cluster solicitation
The new solicitation for architecture proposals to the NSF Computing
Processes and Artifacts (CPA) cluster is up and available at
http://nsf.gov/pubs/2007/nsf07587/nsf07587.htm. The proposal deadline is
December 7, 2007. There are some changes compared to last year's
solicitation, so submitters should carefully read the new solicitation. One
notable change is that an investigator may participate on at most two
proposals (instead of just one) as long as at least one of the proposals is
a "team" or "major team" proposal, but only a few proposals in these
categories are expected to be awarded overall.
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* NSF "Expeditions in Computing" (Expeditions) Solicitation
A new NSF CISE program called "Expeditions in Computing" (Expeditions)
provides the opportunity for the computing research community to pursue
ambitious, compelling, and transformative research agendas that promise
disruptive innovations in the computing and information fields. Funded at
levels up to $2,000,000 per year for five years, awarded projects are
expected to explore far-reaching research and education activities motivated
by hard problems and/or compelling applications. Teams of investigators
from within or across departments or institutions are encouraged to combine
their expertise and talents to forge well-integrated research appropriate
for the Expeditions program. More information about Expeditions is
available at http://nsf.gov/pubs/2007/nsf07592/nsf07592.htm. Note the
following deadlines: a Letter of Intent is due November 5, 2007, and the
Preliminary Proposal is due December 30, 2007. It is estimated that only 20
collaborating teams will be invited to submit a full proposal due on April
1, 2008, with only 3 of those proposals anticipated for award.
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* STAMP Release: Stanford Transactional Applications for Multi-Processing (STAMP)
The TCC group is happy to release the Stanford Transactional Applications for Multi-
Processing (STAMP), a collection of applications well suited for transactional memory
research. STAMP v0.9.0 includes four applications (delaunay, genome, kmeans, and
vacation). For each application, the suite includes sequential code in C, parallel code
that uses coarse-grain transactions, and reference data sets. We provide transactional
code for both hardware (HTM) and software (STM) systems, as well as a reference STM
implementation based on Sun's TL2 [2]. A brief characterization of the applications is
given in [1].
STAMP is available at: http://stamp.stanford.edu
We are currently working on additional STAMP applications and a detailed characterization
report. We welcome your feedback, corrections, and suggestions. If you use STAMP in your
work, please cite [1].
--------------
[1] "An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees,"
Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Bronson,
Jared Casper, Christos Kozyrakis, Kunle Olukotun. Proceedings of the 34th Annual
International Symposium on Computer Architecture, San Diego, California, 9-13 June 2007.
[2] "Transactional Locking II," Dave Dice, Ori Shalev, Nir Shavit Proceedings of the
20th International Symposium on Distributed Computing (DISC), Stockholm, Sweeden,
Sept. 2006.
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* IISWC 2007 Call for Participation: Tenth IEEE Intl Symposium on Workload Characterization
(IISWC 2007)
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C A L L F O R P A R T C I P A T I O N -- I I S W C 2 0 0 7
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We would like to welcome you to participate in the Tenth IEEE Intl Symposium on Workload
Characterization (IISWC 2007)
in Boston, MA, during September 27-29, 2007.
The symposium features an exciting technical conference comprising excellent papers from
a diverse set of areas,two keynote speeches by distinguished speakers, and two tutorials.
A summary of the program appears below and may also be found at:
available at: http://www.iiswc.org.
Please consider attending!
Where: Four Point Sheraton Logan Airport, Boston, MA, USA When: September 27-29 2007
--------------------
Program at a glance
--------------------
Thursday, September 27
8:00 a.m. - 8:30 a.m. Breakfast and Registration
8:30 a.m. - 8:45 a.m. Welcome Remarks
8:45 a.m. - 9:45 a.m. Keynote Speech I
10:15 a.m. - 12:15 p.m. Technical Session: Prediction
and Implications on Application Performance
1:30 p.m. - 3:00 p.m. Technical Session: Multi-core
3:30 p.m. - 4:30 p.m. Technical Session: Benchmark Studies
4:45 p.m. - 6:00 p.m. Panel Session
Friday, September 28
8:00 a.m. - 8:45 a.m. Breakfast
8:45 a.m. -9:45 a.m. Keynote Speech II
10:15 a.m. - 12:15 p.m. Technical Session: Benchmarks
1:30 p.m. - 3:00 p.m. Technical Session: Tracing and Online
Characterization
3:30 p.m. - 4:30 p.m. Technical Session: Data Center Applications
4:30 p.m. - 6:00 p.m. Technical Session: Compact Workload Creation
Saturday, September 29
Morning session Tutorial I
Afternoon session Tutorial II
----------------------------
Deatailed technical program
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Thursday, September 27
8:00 a.m. - 8:30 a.m. Breakfast and Registration
8:30 a.m. - 8:45 a.m. Welcome Remarks
8:45 a.m. - 9:45 a.m. Keynote Speech I
The SPEC Gorilla Turns One. So What?
John Henning, Sun Microsystems
SPEC CPU2006 is a 500 pound gorilla of benchmarking, with 1300 results published since
its release one year ago (24 August 2006), despite consuming vastly more time and
computational resources than its predecessor suites.
What have we learned about its workloads during its first year of life? Are there surprises
lurking in the code, workloads, or run rules that are difficult to simulate? What
characteristics of CPU2006 have proven successful? What does SPEC need to improve in
successor suites? Some proposed answers will be provided and time will be reserved for
an open microphone. The presenter will also be available during breaks to listen to feedback
about the suite.
A collection of eleven technical articles about SPEC CPU2006 will be given away; sit near
the front of the room to improve your chances of receiving a hard copy.
John L. Henning is a Performance Engineer at Sun Microsystems and is Secretary for the
SPEC CPU Subcommittee. He has contributed to performance analysis and improvement of
software on PDP-11, VAX, Alpha, and SPARC systems, including, in 1980, an implementation
of a client/server text processing workload based on observed user workloads. His first
successful performance project was shrinking a SORT process on an IBM 360/30 from 8 hours
to 20 minutes. This speedup was accomplished by improving the match between the user
requirements, the available computational resources, and the workload.
9:45 a.m. - 10:15 a.m. Break
10:15 a.m. - 12:15 p.m. Predicting and Implications on Application
Performance
Characterizing the Effect of Microarchitecture Design Parameters on Workload Dynamic Behavior
Chang-Burm Cho, Wangyuan Zhang, Tao Li, University of Florida
Implications of Conflict Rate Trends for Robust Software Transactional Memory
Craig Zilles, University of Illinois at Urbana-Champaign; Ravi Rajwar, Intel Corporation
Predicting Program Behavior Based On Objective Function Minimization
Ruhi Sarikaya, Alper Buyuktosunoglu, IBM Research
On the Effects of Memory Latency and Bandwidth on Supercomputer Application Performance
Richard C. Murphy, Sandia National Laboratories
12:15 p.m. - 1:30 p.m. Lunch
1:30 p.m. - 3:00 p.m. Multi-core
Evaluation of Server Consolidation Workloads for Multi-core Designs
Natalie Enright Jerger, Dana Vantrease, Mikko H. Lipasti, University of Wisconsin - Madison
Performance Studies of Commercial Workloads on a Multi-core System
Jessica H. Tseng, Hao Yu, Shailabh Nagar, Niteesh Dubey, Hubertus Franke, Pratap Pattnaik,
Hiroshi Inoue, Toshio Nakatani, IBM Research
Addressing Cache/Memory Overheads in Enterprise Java CMP Servers
Kumar Shiv, Mahesh Bhat, Mike Jones, Ramesh Illikal, Srihari Makineni, Don Newell,
Jason Domer, Ravi Iyer, Intel
3:00 p.m. - 3:30 p.m. Break
3:30 p.m. - 4:30 p.m. Benchmark Studies
Benchmarking BGP Routers
Qiang Wu, Yong Liao, Tilman Wolf, Lixin Gao, University of Massachusetts
Characterizing and Improving the Performance of Bioinformatics Workloads on the POWER5
Architecture
Vipin Sachdeva, Evan Speight, Mark W. Stephenson, IBM Research; Lei Chen, IBM Systems and
Technology Group
4:45 p.m. - 6:00 p.m. Panel Session
Benchmarking in the Web 2.0 Era
Moderator: Sudhanva Gurumurthi, University of Virginia
Friday, September 28
8:00 a.m. - 8:45 a.m. Breakfast
8:45 a.m. - 9:45 a.m.
Keynote Speech II
Taking Concurrency Seriously: the Multicore Challenge
Maurice Herlihy, Brown University
Computer architecture is undergoing, if not another revolution, then a vigorous shaking-up.
The major chip manufacturers have, for the time being, simply given up trying to make
processors run faster. Instead, they have recently started shipping "multicore''
architectures, in which multiple processors (cores) communicate directly through shared
hardware caches, providing increased concurrency instead of increased clock speed. As a
result, system designers and software engineers can no longer rely on increasing clock
speed to hide software bloat. Instead, they must somehow learn to make effective use of
increasing parallelism. This adaptation will not be easy. Conventional synchronization
techniques based on locks and conditions are unlikely to be effective in such a demanding
environment.
Transactional memory is a computational model in which threads synchronize by transactions.
This synchronization model promises to alleviate many (perhaps not all) of the problems
associated with locking, and there is a growing community of researchers working on both
software and hardware support for this approach. This talk will survey the area, with a
focus on open research problems.
Maurice Herlihy has an A.B. in Mathematics from Harvard University and a Ph.D. in Computer
Science from MIT. He has been an Assistant Professor in the Computer Science Department at
Carnegie Mellon, a member of research staff at Digital Equipment Corporation's
Cambridge (MA) Research Lab, and a consultant for Sun Microsystems. He is now a Professor
of Computer Science at Brown University. His 1991 paper "Wait-Free Synchronization" won
the 2003 Dijkstra Prize in Distributed Computing, and he shared the 2004 Goedel Prize for
his 1999 paper "The Topological Structure of Asynchronous Computation." He is a Fellow of
the ACM.
9:45 a.m. - 10:15 a.m. Break
10:15 a.m. - 11:45 a.m. Benchmarks
Session Chair: Lieven Eeckhout, Ghent University
Pynamic: The Python Dynamic Benchmark Behavior
G. L. Lee, D. H. Ahn, B. R. de Supinski, J. Gyllenhaal, P. Miller, Lawrence Livermore
National Laboratory
Delaunay Triangulation with Transactions and Barriers
M. L. Scott, M. F. Spear, L. Dalessandro, V. J. Marathe, University of Rochester
FacePerf: Benchmarks for Face Recognition Algorithms
D. S. Bolme, M. Strout, J. R. Beveridge, Colorado State University
HD-VideoBench: A Benchmark for Evaluating High Definition Digital Video
M. Alvarez, E. Salami, A. Ramirez, M. Valero, UPC and BSC
11:45 a.m. - 1:30 p.m. Lunch
1:30 p.m. - 3:00 p.m. Tracing and Online Characterization
Seekable Compressed Traces
Tip Moseley, Dirk Grunwald, University of Colorado at Boulder; Ramesh Peri, Intel
Analysis of Statistical Sampling in Microarchitecture Simulation: Metric, Methodology,
and Program Characterization
Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Wei-Chung Hsu, Pen-Chung Yew,
University of Minnesota
Efficient Disk I/O Characterization using Online Histograms in a Virtual Machine Hypervisor
Irfan Ahmad, VMware
3:00 p.m. - 3:30 p.m. Break
3:30 p.m. - 4:30 p.m. Data Center Applications
An Observation-Based Approach to Performance Characterization of Distributed n-Tier
Applications
Calton Pu, Akhil Sahai, HP Labs; Jason Parekh, Gueyoung Jung, Ji Bae, You-Kyung Cha,
Timothy Garcia, Danesh Irani, Jae Lee, Qifeng Lin, Georgia Institute of Technology
Workload Anaysis and Demand Prediction of Enterprise Data Center Applications
Daniel Gmach, Technische Universitat Munchen; Jerry Rolia, Ludmila Cherkasova, HP Labs;
Alfons Kemper, Technische Universitat Munchen
4:30 p.m. - 6:00 p.m.
Compact Workload Creation
SCRAP: A Statistical Approach for Creating Compact Representational Query Workload based
on Performance Bottlenecks
James A. Skarie, Biplob K. Debnath, David J. Lilja, Mohamed F. Mokbel, University of
Minnesota
Representative Multiprogram Workloads for Multithreaded Processor Simulation
Michael Van Biesbrouck, UCSD; Lieven Eeckhout, Ghent University; Brad Calder, UCSD,
Microsoft
Hierarchical Means: Single Number Benchmarking with Workload Cluster Analysis
Richard M. Yoo, Hsien-Hsin S. Lee, Georgia Tech.; Han Lee, Kingsum Chow, Intel
Best regards,
Bhuvan Urgaonkar
(for IISWC 2007)
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* INA-OCMC Call for Papers: Interconnection Network Architectures: On-Chip, Multi-Chip
CALL FOR PAPERS
Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC)
(http://www.disca.upv.es/jflich/wina/wina.html)
Held in conjunction with
the 3rd International Conference on High-Performance Embedded
Architectures and Compilers (HiPEAC) (http://www.hipeac.net/conference)
in Goteborg, Sweden, January 27, 2008
Organizers:
- Jose Duato, Technical University of Valencia, Spain (General Co-Chair)
- Jose Flich, Technical University of Valencia, Spain (General Co-Chair)
- Olav Lysne, Simula Research Laboratory, Norway (Program Chair)
The solutions for communication between components within embedded
and parallel systems is undergoing rapid development. The move to
multi-core chips force programmers to develop parallel applications,
and thus demand novel solutions to how cores on a chip should communicate
between them. At the other end of the scale, parallel supercomputers
with tens of thousands of processors demand new and scalable solutions
to interconnections of its components.
This workshop concerns the architecture of interconnection
switches or routers, and networks of switches or routers, whether
on-chip or multi-chip.� Topics of interest, within the context of
interconnection networks, include but are not limited to:
* Networks-on-Chip (NoC)
* Multi-Chip Interconnection Networks, including Cluster Interconnects
* "Commodity Switches" as general-purpose building blocks
* Switching, buffering, and routing architectures
* Flow control and congestion management in switching fabrics
* Virtualization
* Topology exploration
* Timing, synchronous/asynchronous communication
* Reliability, availability, fault tolerance
* Area/power versus functionality/QoS support in NoC architectures
* Design space exploration
The goal of the workshop is to provide a forum for presenting and
discussing mostly work in progress, or ideas for future research
in response to future trends. The workshop intends to include a
couple of presentations by experts in the field about the current
state-of-the-art and where we need to go, and intends to encourage
discussions among the participants. It does not matter if the
views and opinions expressed are "wild and crazy", as long as they
have been carefully thought out and they are intuitively sound
and implementable.
This is the second year of the workshop. In its first year the workshop
exhibited a high audience and interesting discussions arose from the different
presentations of authors.
Program Committee:
- Olav Lysne, Simula Research Laboratory
- Francisco Alfaro, UCLM, Spain
- Luca Benini, University of Bologna, Italy
- Davide Bertozzi, University of Bologna, Italy
- Ulrich Bruning, U. Mannheim, Germany
- Ran Ginosar, Technion, Israel
- Kees Goossens , NXP and T.U.Delft, The Netherlands
- Wojciech Kabacinski, Poznan University of Technology, Poland
- Manolis Katevenis, FORTH, Greece
- Hugo Kohmann, Dolphin Interconnect Solutions, Norway
- Cyriel Minkenberg, IBM Zurich Research Laboratory, Switzerland
- Robert Mullins, Cambridge University, United Kingdom UK
- Dionisios Pnevmatikatos, FORTH-ICS and Techn. Univ. of Crete, Greece
- Jose Luis Sanchez, UCLM, Spain
- Thomas Sodring, Simula Research Laboratory, Norway
- Ola Torudbakken, SUN, Norway
Submissions and acceptance will be in the form of extended abstracts
of length 3-5 pages. The submission procedure will be through the EDAS
web-page (http://www.disca.upv.es/jflich/wina/wina.html). There will be no Proceedings,
but we will encourage authors to electronically share their texts
and slides with all participants.
Important dates:
- Submission deadline: Oct 15, 2007
- Notification to authors: Dec 1, 2007
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* Computing Frontiers 2008 Call for Papers: 2008 ACM International Conference on Computing
Frontiers
=================================================================
Call for Papers
2008 ACM International Conference on Computing Frontiers
(Computing Frontiers 2008)
May 5-7, 2008, Ischia, Italy
http://www.computingfrontiers.org/
Sponsored by:
Association for Computing Machinery <http://www.acm.org/>
ACM Special Interest Group on Microarchitecture <http://www.acm.org/sigmicro>
=================================================================
Call for Papers - Computing Frontiers 2008
The increasing needs of present and future computation-intensive
applications have stimulated research in new and innovative approaches
to the design and implementation of high-performance computing systems.
These boundaries between state of the art and innovation constitute the
computing frontiers that must be pushed forward to provide the
computational support required for the advancement of all science
domains and applications. This conference focuses on a wide spectrum of
advanced technologies and radically new solutions; it is designed to
foster communication among many scientific and technological disciplines.
Authors are invited to submit papers on all areas of innovative
computing systems that extend the current frontiers of computer science
and engineering and that will provide advanced systems for current and
future applications.
Papers are sought on theory, methodologies, technologies, and
implementations concerned with innovations in computing paradigms,
computational models, architectural paradigms, computer architectures,
development environments, compilers, and operating environments. Papers
should be submitted to one of the following areas:
* Non-conventional computing
* Next-generation high performance computing
* Virtualization and virtual machines
* Grid computing
* Compilers and operating systems
* Workload characterization of emerging applications
* Service oriented architecture (SOA) and system impact
* Supercomputing
* SOC architectures, embedded architectures and special purpose
architectures
* Temperature, energy, and complexity-aware designs
* System management and security
* Quantum computing
* Computational biology
* Reconfigurable computing
* Autonomic and organic computing
* Computation intelligence frontiers: theory and industrial
applications
* Fault tolerance and Reliability
=========================================================
Computing Frontiers 2008 Committee Information
=========================================================
* General Chair: Alex Ramirez, Universitat Politecnica de Catalunya (UPC)
* Program Chair: Michael Gschwind, IBM TJ Watson Research Center
* Program Co-Chair: Gianfranco Bilardi, University of Padova
=========================================================
Important dates
=========================================================
* Paper submission: *December 7, 2007*
* Author notification: *January 18, 2008*
* Final papers due: *February 22, 2008*
=========================================================
Forms / downloads
=========================================================
* Call For Papers (pdf) http://www.computingfrontiers.org/docs/cf08_cfp.pdf
=========================================================
Sponsors
=========================================================
Association for Computing Machinery <http://www.acm.org/>
ACM Special Interest Group on Microarchitecture <http://www.acm.org/sigmicro>
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* ASPLOS-XIII Call for Workshops and Tutorials
Title: ASPLOS-XIII Call for Workshops and Tutorials
URL: http://research.microsoft.com/asplos08
Proposals are being solicited for workshops and tutorials to be help in conjunction with
ASPLOS-XIII. Please keep in mind that the goal of workshops and tutorials is to foster
discussion on new topics in emerging areas. Also, that a major characteristic should be
a high level of interactivity. Please choose the workshop and tutorial topics and format
accordingly. Proposals due by October 1, 2007. More information and instructions for
submitting a proposal are available on the ASPLOS web site:
http://research.microsoft.com/asplos08/workshops.htm
http://research.microsoft.com/asplos08/tutorials.htm
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* ACM - INFOSYS FOUNDATION AWARD
ACM - INFOSYS FOUNDATION AWARD
NOMINATIONS SOLICITED
Nominations are invited for the 2007 ACM ? Infosys Foundation Award. The ACM - Infosys
Foundation Award in the Computing Sciences recognizes personal contributions by young
scientists and system developers to a contemporary innovation that, through its depth,
fundamental impact and broad implications, exemplifies the greatest achievements in the
discipline. The award is accompanied by a prize of $150,000. Financial support for the
award is provided by an endowment from the Infosys Foundation.
Nominations should include:
1. A current vitae, listing the age of the candidate, publications, patents, honors
other awards, etc.
2. A nomination letter from the principal nominator, which describes the work of the
nominee, and draws particular attention to the contributions which are seen as
meriting the award.
3. Short supporting letters from at least three, and no more than five, endorsers.
The letters should come from prominent individuals familiar with the nominee's
contributions and no more than two from the same institution.
For additional information on ACM's award program please visit:
http://awards.acm.org/html/awards.cfm
Nominations should be sent to the Chair of the ACM ? Infosys Foundation Award by
December 31, 2007:
Juris Hartmanis
jh@xxxxxxxxxxxxxx
In addition to Dr. Hartmanis, the ACM ? Infosys Foundation Award Committee members are
Susan Graham, Butler Lampson, Kurt Mehlhorn, Amit Singhal, and Andrew Yao.
For additional information please see the press release:
http://www.acm.org/news/featured/press-room/news-releases/infosys
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