Date: | Thu, 31 Aug 2006 10:25:04 -0500 (CDT) |
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From: | Mike Marty <mikem@xxxxxxxxxxx> |
Subject: | Re: [Gems-users] Ruby statistics - No L1 cache miss ??? |
> This purpose is to allow the L1 controller to see *all* L1 cache accesses > including hits. > The above purpose is with REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH set to true, the below is with it set to false > The purpose also allows the SMP/single-controller protocols to model a > different L1 and L2 hit latency. In these protocols, a single controller > models both the L1 and L2 cache controllers. Thus fast-path must be > enabled so that any hit to a controller is assumed to be an L1 miss but L2 > hit. > You should only set this to true if you are using a CMP protocol with split L1 and L2 controllers. |
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