Thanks Mike,
Best Regards,
Derin Harmanci.
Quoting Mike Marty <mikem@xxxxxxxxxxx>:
> This purpose is to allow the L1 controller to see *all* L1 cache accesses
> including hits.
>
> The purpose also allows the SMP/single-controller protocols to model a
> different L1 and L2 hit latency. In these protocols, a single controller
> models both the L1 and L2 cache controllers. Thus fast-path must be
> enabled so that any hit to a controller is assumed to be an L1 miss but L2
> hit.
>
> --Mike
>
> >
> > Thank you very much for the reply. By the way, is the parameter
> > REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH for the statistic of L1 cache
> misses
> > or it is there for another purpose?
> >
> > Derin Harmanci.
> >
> > Quoting Mike Marty <mikem@xxxxxxxxxxx>:
> >
> > >
> > > The L1 misses statistic is currently set in the Ruby Sequencer by
> directly
> > > accessing the CacheMemory objects to test for a hit. By setting
> > > "REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH" to true, you remove this check
> and
> > > L1 misses is all 0.
> > >
> > > --Mike
> > >
> > >
> > > >
> > > > Hello,
> > > >
> > > >
> > > > > The statistic might not be hooked up to the particular protocol you
> are
> > > > > simulating.
> > > >
> > > >
> > > > How can I find out if it is the case? I'm using the MOSI_SMP_bcast
> > > protocol,
> > > > the one which is given as an example in the Wiki Quickstart page.
> Also,
> > > > I have set the following set of parameters (at runtime) as follows:
> > > >
> > > > ruby0.setparam g_RANDOM_SEED 1
> > > > ruby0.setparam g_trace_warmup_length 1000000
> > > > ruby0.setparam SIMICS_RUBY_MULTIPLIER 2
> > > > ruby0.setparam OPAL_RUBY_MULTIPLIER 1
> > > > ruby0.setparam_str REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH true
> > > >
> > > > ruby0.setparam L1_CACHE_ASSOC 2
> > > > ruby0.setparam L1_CACHE_NUM_SETS_BITS 7
> > > > ruby0.setparam L2_CACHE_ASSOC 4
> > > > ruby0.setparam L2_CACHE_NUM_SETS_BITS 13
> > > >
> > > > ruby0.setparam g_MEMORY_SIZE_BYTES 4294967296
> > > > ruby0.setparam g_DATA_BLOCK_BYTES 128
> > > > ruby0.setparam g_PAGE_SIZE_BYTES 4096
> > > > ruby0.setparam g_NUM_PROCESSORS 1
> > > > ruby0.setparam g_NUM_L2_BANKS 0
> > > > ruby0.setparam g_NUM_MEMORIES 0
> > > > ruby0.setparam g_PROCS_PER_CHIP 1
> > > >
> > > > ruby0.setparam NULL_LATENCY 0
> > > > ruby0.setparam NETWORK_LINK_LATENCY 4
> > > > ruby0.setparam CACHE_RESPONSE_LATENCY 12
> > > > ruby0.setparam MEMORY_RESPONSE_LATENCY_MINUS_2 268
> > > > ruby0.setparam DIRECTORY_LATENCY 2
> > > > ruby0.setparam DIRECTORY_CACHE_LATENCY 1
> > > >
> > > > ruby0.setparam ON_CHIP_LINK_LATENCY 1
> > > > ruby0.setparam RECYCLE_LATENCY 10
> > > > ruby0.setparam TIMER_LATENCY 10000
> > > >
> > > > ruby0.setparam_str PERIODIC_TIMER_WAKEUPS true
> > > >
> > > > ruby0.setparam L1_REQUEST_LATENCY 3
> > > > ruby0.setparam L2_REQUEST_LATENCY 5
> > > > ruby0.setparam L2_RECYCLE_LATENCY 5
> > > >
> > > > ruby0.setparam SEQUENCER_TO_CONTROLLER_LATENCY 2
> > > >
> > > >
> > > >
> > > > ruby0.setparam g_SEQUENCER_OUTSTANDING_REQUESTS 8
> > > >
> > > > ruby0.setparam NUMBER_OF_TBES 16
> > > > ruby0.setparam NUMBER_OF_L1_TBES 16
> > > > ruby0.setparam NUMBER_OF_L1_TBES 16
> > > >
> > > >
> > > >
> > > > ruby0.setparam_str FINITE_BUFFERING false
> > > > ruby0.setparam FINITE_BUFFER_SIZE 0
> > > > ruby0.setparam PROTOCOL_BUFFER_SIZE 2
> > > >
> > > >
> > > >
> > > > ruby0.setparam_str g_NETWORK_TOPOLOGY HIERARCHICAL_SWITCH
> > > > ruby0.setparam_str g_CACHE_DESIGN NUCA
> > > > ruby0.setparam g_NUM_DNUCA_BANK_SETS 8
> > > > ruby0.setparam g_NUM_DNUCA_BANK_SET_BITS 0
> > > > ruby0.setparam NUMBER_OF_VIRTUAL_NETWORKS 4
> > > > ruby0.setparam FAN_OUT_DEGREE 4
> > > > ruby0.setparam_str g_PRINT_TOPOLOGY true
> > > >
> > > >
> > > > Is there something wrong with those parameters?
> > > >
> > > > By the way, what does a TBE mean (Sorry for the ignorance)
> > > > Is it tag memory, the TLB ?
> > > >
> > > > One more small question. How can we configure the intra-chip
> > > > network? From the ISCA slides I understand that Ruby generates
> > > > a single central switch to connect all intra chip components.
> > > > Is it always the case, or can we configure this network to be
> > > > something else? (By the way, where is the this central switch
> > > > defined, in which file/object can I find this switch?)
> > > >
> > > > Any help will be very much appretiated.
> > > >
> > > > Thanks,
> > > >
> > > > Derin Harmanci
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > > >
> > > > > >
> > > > > > I'm running a simple application on simics and getting memory
> > > system
> > > > > > statistics with Ruby. I'm using a system with L1 and L2 caches
> where
> > > > > > g_CACHE_DESIGN parameter is set to NUCA. However, I do not get
> any
> > > L1
> > > > > > cache misses. All the misses that are counted are seen as L2
> cache
> > > > > > misses.
> > > > > > and there is no L1 cache miss !!! What can be wrong in my
> setting?
> > > > > > Can it be something in setting Ruby parameters? Any help will be
> > > > > > appreciated.
> > > > > >
> > > > > > Thanks,
> > > > > >
> > > > > > Derin Harmanci
> > > > > > _______________________________________________
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