Re: [Gems-users] Relation between SIMICS cycle & GEMS cycle

["Weihang Jiang" <weihang.jiang@xxxxxxxxx>]

On 3/30/06, Min Xu (Hsu) <xu@xxxxxxxxxxx> wrote:
> On Thu, 30 Mar 2006 Weihang Jiang wrote :
> > Hi Min,
> >     Thank you for your comments. Yes, only modifying tick/stick
> > registers does not make system behavior 100% consistent with GEMS
> > timing. But the bottom line is, it can enable the system level
> > profiling tools(e.g. DTrace) to reflect on GEMS timing. Otherwise, we
> > need to do the same jobs inside GEMS to profile system behavior.
>
> I see, this makes sense. Can you give an example profiling task
> that is easy to do in DTrace and harder to do in GEMS?

I think nothing essential prevents us from gathering all the
information DTrace can provide inside GEMS. But, DTrace offers more
than 30,0000 monitoring points in the kernel. And I heard DTrace is
not intrusive.


>
> > Secondly, it will reduce the frequency of interrupt handlers, which
> > are relying tick,stick,tick_cmp,stick_cmp registers.
>
> This surprises me. Can you point me to the document that describes
> how interrupt frequency is relying on these registers?
>
>

In UltraSparc III User manual, Section 6.7.4,  Timer State Register,
it describes something about it. It just affects soft interrupt rate.

http://www.sun.com/processors/manuals/USIIIv2.pdf


--
Weihang Jiang