Re: [Gems-users] Relation between SIMICS cycle & GEMS cycle

["Weihang Jiang" <weihang.jiang@xxxxxxxxx>]

On 3/30/06, Min Xu (Hsu) <xu@xxxxxxxxxxx> wrote:
> On Thu, 30 Mar 2006 Weihang Jiang wrote :
> > On 3/30/06, Min Xu (Hsu) <xu@xxxxxxxxxxx> wrote:
> > > I see, this makes sense. Can you give an example profiling task
> > > that is easy to do in DTrace and harder to do in GEMS?
> >
> > I think nothing essential prevents us from gathering all the
> > information DTrace can provide inside GEMS. But, DTrace offers more
> > than 30,0000 monitoring points in the kernel. And I heard DTrace is
> > not intrusive.
>
> You are right. Some tasks are perhaps much easier in DTrace than
> in GEMS.
>
> > > This surprises me. Can you point me to the document that describes
> > > how interrupt frequency is relying on these registers?
> >
> > In UltraSparc III User manual, Section 6.7.4,  Timer State Register,
> > it describes something about it. It just affects soft interrupt rate.
> >
> > http://www.sun.com/processors/manuals/USIIIv2.pdf
>
> Thanks. I didn't know this before. In simics, however, I suspect
> you cannot just modify the registers and expect things will work out.
> (e.g., you can change the tick register from 100-simics-time to
> 200-gems-time when solaris reads the register. Then solaris write
> the tick_compare with 200-gems-time + 100-gems-time=300-gems-time.
> But simics will interrupt at 300-simics-time, which might be
> 500-gems-time.)

Why do you think so? It says, "The TICK_COMPARE register causes the
processor to generate a trap when the TICK register reaches the value
in the TICK_COMPARE register  ... ". So, if we keep updating the
values of TICK register at the end of each GEMS cycle, the interrupt
will be correctly triggered based on GEMS time.

STICK/STICK_COMPARE work in the same way.


>I still think you need to modify the simics cycle
> count, which is perhaps used to generate the value in the tick
> registers in the first place.
>

I agree on this. But I have no idea how to achieve this. Maybe we can
delay some cycles for each instructions to make SIM cycles == GEMS
cycles.


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--
Weihang Jiang