Re: [Gems-users] CPU accesses to L2 cache


Date: Sat, 28 Oct 2006 09:52:09 +0200
From: "Daniele Bordes" <daniele.bordes@xxxxxxxxx>
Subject: Re: [Gems-users] CPU accesses to L2 cache
Thank you for your quick and exhaustive reply, Dan. I try to answer
your questions:

 cpu0 is probably active only to respond to your keypresses and to fork
  your processes (ps -A, prstat, etc).

Perhaps it is so, but I stop Simics simulation (ctrl+c) and type
Ruby0.dump-stats when no commands are in execution.

Also, did you issue instruction-fetch-mode instruction-fetch-trace,
istc-disable, dstc-disable to Simics?

Yes, I use those commands

Try running a mulitthreaded benchmark, and be sure to use
processor_bind() to get all the processors busy.


Well, the fact is that I first noticed the "strange" statistics just
when I tried to run some OCEAN multithreaded simulations with one
thread per CPU (using processor_bind() ), and I hoped that in an "idle
machine" case the situation was different, but it's the same.
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