Re: [Gems-users] CPU accesses to L2 cache

[Dan Gibson <degibson@xxxxxxxx>]

Daniele Bordes wrote:

Thank you for your quick and exhaustive reply, Dan. I try to answer
your questions:

  

 cpu0 is probably active only to respond to your keypresses and to fork
  your processes (ps -A, prstat, etc).
    

Perhaps it is so, but I stop Simics simulation (ctrl+c) and type
Ruby0.dump-stats when no commands are in execution.
  

dump-stats reports the stats for the entire execution history.

Also, did you issue instruction-fetch-mode instruction-fetch-trace,
istc-disable, dstc-disable to Simics?
    

Yes, I use those commands
  

How about cpu-switch-time 1?

Try running a mulitthreaded benchmark, and be sure to use
processor_bind() to get all the processors busy.

    

Well, the fact is that I first noticed the "strange" statistics just
when I tried to run some OCEAN multithreaded simulations with one
thread per CPU (using processor_bind() ), and I hoped that in an "idle
machine" case the situation was different, but it's the same.
  

Did you run the benchmark for long time? Did you start ruby after the processor_bind() calls to avoid the single-cpu startup transient?

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