| It depends partially on where you want to put the hardware components, and what the components plan on doing. From what i've gathered, L1 is checked for the data in Sequencer's call to doRequest (hit=tryCacheAccess .. .). If there is a hit, it will go through the fast cache access path. If not the issueRequest function will be called which will queue up the access for the L2. It than adds on latency and puts it into the queue. If you wanted the hardware to go between the L1 access and L2 hardware you could call a different function besides issue request, and do your work on the new hardware in there. After that you could then call issueRequest on the data. You should even be able to add latency at that point (separate from the SEQUENCER_TO_CONTROLLER_LATENCY), but the handling of that I am unsure of.
I am currently looking to use a similar method to bypass L1 cache under certain instances, but so far I haven't tested too much of this. Mike, correct me if I'm wrong with any of this.
Phil On Jul 26, 2006, at 2:06 PM, Dave wrote: Is this not doable in GEMS?
Thank you.
Dave <zhu_dave@xxxxxxxxx> wrote: Hello,
I would like to ask a few questions regarding Ruby's extensibility. I would like to add a few hardware components to the memory hierarchy, but I am not sure what files to modify. The files under ruby/system seem to be a good starting point. Then, I can add a few coherence states using SLICC. As I understand ruby/system/sequencer handles requests between the driver and L1 controller. What does the driver refer to? How about requests between L1 controller and L2 controller? What if I add a hardware component between L1 cache and L2 cache? What files should I modify? Are there any examples/demos that show several configurations? Or is there any documentation on how to add new components to the Ruby system?
Any help will be greatly appreaciated.
Thank you.
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