> It depends partially on where you want to put the hardware
> components, and what the components plan on doing.
You are right in that it entirely depends on what is being added.
> From what i've
> gathered, L1 is checked for the data in Sequencer's call to doRequest
> (hit=tryCacheAccess .. .). If there is a hit, it will go through the
> fast cache access path.
This is indeed the case for SMP protocols where fast paths are required in
order for a single controller, that handles both the L1 and L2 cache, to
distinguish between an L1 hit and an L2 hit
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