Re: [Gems-users] A question in LogTM

[Mike Marty <mikem@xxxxxxxxxxx>]

Yes, a good observation of a flaw that will be fixed shortly.  The LogTM
requires the fast path to be disabled so that R/W bits are set.  But since
the released LogTM protocol is an SMP with combined L1/L2 controllers, by
disabling fast path, the L1 timing is disabled as well.

We will release a fix to this shortly (along with a LogTM CMP protocol).
If you need a faster fix or workaround, one of the LogTM people might be
able to chime in and help you.

--Mike

> When an ld_xact/st_xact hits in a fast path, the request never goes to Cache
> Controller. The question is that, in such a situation, how the simulator
> sets up the R/W bit for the corresponding cache line? It seems that the
> simulator leaves the flag unchanged--be a big bug? If the problem do exists,
> how to get a quick fix?
>
> G.R.
>
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