Re: [Gems-users] A question in LogTM

[郭锐 <timmyguo@xxxxxxxxxxxxxxxx>]

Thanks for confirming this bug.
My suggestion is that why not deal with R/W bit in
CacheMemory::tryCacheAccess()?
By disabling fast path, all transaction load/stores need extra cycles to
complete. It will be a big penalty and may kill much of the speedup of
LogTM.
In fact the same problem exists not only for LogTM. Any fast path store
fails to setup the 'Dirty' bit just as the R/W bit problem here.

Regards
G.R.

> -----Original Message-----
> From: gems-users-bounces@xxxxxxxxxxx
[mailto:gems-users-bounces@xxxxxxxxxxx]
> On Behalf Of Mike Marty
> Sent: Sunday, January 21, 2007 2:02 AM
> To: Gems Users
> Subject: Re: [Gems-users] A question in LogTM
> 
> Yes, a good observation of a flaw that will be fixed shortly.  The LogTM
> requires the fast path to be disabled so that R/W bits are set.  But since
> the released LogTM protocol is an SMP with combined L1/L2 controllers, by
> disabling fast path, the L1 timing is disabled as well.
> 
> We will release a fix to this shortly (along with a LogTM CMP protocol).
> If you need a faster fix or workaround, one of the LogTM people might be
> able to chime in and help you.
> 
> --Mike
> 
> > When an ld_xact/st_xact hits in a fast path, the request never goes to
Cache
> > Controller. The question is that, in such a situation, how the simulator
> > sets up the R/W bit for the corresponding cache line? It seems that the
> > simulator leaves the flag unchanged--be a big bug? If the problem do
exists,
> > how to get a quick fix?
> >
> > G.R.
> >
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