Re: [Gems-users] A question in LogTM

[郭锐 <timmyguo@xxxxxxxxxxxxxxxx>]

Thanks again for your reply. I had made a quick and dirty fix in my
suggested way. 
It seems to work. But I am still looking forward to your update.

> > In fact the same problem exists not only for LogTM. Any fast path store
> > fails to setup the 'Dirty' bit just as the R/W bit problem here.
> >
> 
> The dirty bit should indeed get set because it won't be a fast-path store
> (tryCacheAccess should return false if the line isn't dirty).  I agree
that
> it seems checking the R/W bit here would too make sense, but I am really
not
> familiar with the SMP LogTM implementation.

Agree! I missed the point and messed it with the situation of TM.

> 
> I think the whole idea of fast-path was a bad idea and a kludge to allow a
> single controller for both the L1 and L2.  Fortunately for the CMP
> protocols, which are more relevant nowadays, fast-path is not needed.

Yes, I also think the cache structure modeled by ruby is quite confusing at
first.
In addition to a shared controller, the L1 & L2 are exclusive rather than
inclusive.
It's quite strange to me. Sorry for my ignorant.
One more question, why did you say that CMP don't need fast path?
> 
> 
> 
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