Re: [Gems-users] Necessity of NP state

["Juyoung Jung" <juyoung.jung@xxxxxxxxx>]

Mike,


Your explanation is so helpful for me. Thanks a lot, Mike.
By the way, I have another quick question of cache replacement operation. 
Looking into MESI_SCMP_tiledL2bank_directory-
L1cache.sm file, I saw that cache state will change to Invalid state when any cache line in shared(S) or exclusive(M) state encounters L1_Replacement event. However, cache replacement operation should entail getting missed line, and thus I guess the updated line should eventually be marked as non invalid state such as S or M. Please look at the below code from L1 cache controller sm file.

For example, for a case of line replacement in M state, state transition will be "Exclusive state --> transient state waiting for ack --> Invalid state" according to 
transition(M, L1_Replacement, M_I) {
     i_allocateTBE;
     g_issuePUTX;   // send data, but hold in case forwarded request (but clean data not sent)
     ff_deallocateL1CacheBlock;
   }

 transition(M_I, WB_Ack, I) {
     s_deallocateTBE;
     o_popIncomingResponseQueue;
   }

transition(S, L1_Replacement, I) {
     gs_issuePUTS;
     ff_deallocateL1CacheBlock;
   }


When the modified cache line to replace receives acknowledgement for write-back completion, it terminates its replacement operation by marking cache line as Invalid. 
I think further operation may be needed to get new block after receiving WB_Ack; Shouldn't lower-level memory fill the missed line with the required data? (This situation is also shown from cache replacement in S state.) 
Does Ruby decouple cache line replacement from processor reference such Load and Store? If I have wrong thought, please disabuse me. 
Thank you.




Regards,

Young