This is the 2nd March 2007 Digest of SIGARCH Messages (sigarch-mar07b):
* ASPLOS 2008 Call for Papers: Thirteenth International Conference on Architectural Support
for Programming Languages and Operating Systems
http://research.microsoft.com/asplos08/
Submitted by Jim Larus <larus@xxxxxxxxxxxxx>
* TRIPS Toolchain Released for Research Use
http://www.cs.utexas.edu/~trips/ttools-req
Submitted by Doug Burger <dburger@xxxxxxxxxxxxx>
* IISWC 2007 Call for Benchmarks: The Annual 2007 IEEE International Symposium on Workload
Characterization
http://www.iiswc.org/
Submitted by Bhuvan Urgaonkar <bhuvan@xxxxxxxxxxx>
* ISPASS-2007 Call for Participation: International Symposium on Performance
Analysis of Systems and Software
http://www.ispass.org
Submitted by Gabriel Loh <loh@xxxxxxxxxxxxx>
* WDDD 2007 Call for Papers: Workshop on Duplicating, Deconstructing, and Debunking
http://www.ece.wisc.edu/~wddd
Submitted by Trey Cain <tcain@xxxxxxxxxx>
* MoBS 2007 Call for Papers: Workshop on Modeling, Benchmarking, and Simulation
http://www.arctic.umn.edu/~jjyi/MoBS
Submitted by Joshua J. Yi <jjyi@xxxxxxxxxxx>
* Power.org DevCon 07 Call for Papers: Power Architecture Developer Conference 2007
http://www.power.org/devcon/07/callforpapers/
Submitted by Ross Dickson <dickson@xxxxxxxxxxx>
* CRA-W/CDC Programming Languages Summer School Workshop
http://www.cs.utexas.edu/users/mckinley/pl-summer-2007/
Submitted by Kathryn McKinley <mckinley@xxxxxxxxxxxxx>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@xxxxxxx
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Doug Burger Office: 3.432 ACES
Associate Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
The University of Texas at Austin Fax: 512-232-1413
1 University Station, #C0500 E-mail: dburger@xxxxxxxxxxxxx
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* HOTCHIPS 19 Call for Papers: A Symposium on High-Performance Chips (HOTCHIPS - 2007)
A Symposium on High-Performance Chips - HOT CHIPS 19 -
Stanford University, Palo Alto, California
August 19-21, 2007(tentative)
AUTHOR'S SCHEDULE
Deadline for submissions: March 25, 2007
Notification of acceptance: April 30, 2007
Deadline for final version: July 13, 2007
AREAS OF INTEREST:
? Microprocessors ? Novel chips: quantum computing,
? Systems-on-chip nano-structures, micro-arrays
? Embedded processors ? Low-power chips/Dynamic power management
? Chipset chips ? Graphics/Multimedia/Game processors/
? Digital signal processors Display technology
? Application-specific processors ? Advanced semiconductor process technology
? Communication/networking chips ? Reconfigurable chips/processors
? Wireless LAN/Wireless WAN chips ? Operating system/chip interaction
? Network/security processors ? Advanced packaging technology
? Chips built from FPGAs ? Reliability and design for test
? Compiler technology ? Performance evaluation
AUTHOR INFORMATION AND FORMAT
Presentations at HOT Chips are in the form of 30-minute talks. Presentation slides will be
published in the HOT Chips Proceedings. Participants are not required to submit written
papers, but a select group will be invited to submit a paper for inclusion in a special
issue of IEEE Micro.
Submissions must consist of a title, extended abstract (two pages maximum.), and the
presenter's contact information (name, affiliation, job title, address, phone(s), fax,
and email). Please indicate whether you have submitted, intend to submit, or have already
presented or published a similar or overlapping submissionto another conference or journal. Also indicate if you would like the submission to be held
confidential; we do our best to maintain confidentiality if requested.
Submissions should be in plain ASCII text, pasted into the message; do not submit .doc
files, .txt files, MIME'd email, any attachments or other formats. Submissions containing
figures may be submitted in pdf, but plain ASCII text is strongly preferred.
Submissions are evaluated by the Program Committee on the basis of performance of the
device(s), degree of innovation, use of advanced technology, potential market significance,
and anticipated interest to the audience. Research and software contributions will be
evaluated with similar criteria.
Please mail your submissions in plain ASCII text (in the message, not as an attachment!) by
March 25, 2007 to: submit2007@xxxxxxxxxxxx Authors will be notified as to acceptance by
April 30, 2007. Send questions relating to the program to the program chairs at:
program2007@xxxxxxxxxxxx and questions relating to conference operation or organization to
the general chair, John Sell, at: info2007@xxxxxxxxxxxx .
Program Committee Co-Chairs:
John Mashey, Techviser
Raj Amirtharajah, UC Davis
Sponsored by the Technical Committee on Microprocessors and Microcomputers of the
IEEE Computer Society.
Check the HOT CHIPS 19 web page for updates: http://www.hotchips.org
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* ASPLOS 2008 Call for Papers: Thirteenth International Conference on Architectural Support
for Programming Languages and Operating Systems
Thirteenth International Conference on Architectural Support for Programming Languages and Operating Systems
(ASPLOS '08)
The ASPLOS XIII organizing committee is pleased to announce that the ASPLOS XIII conference will be held in Seattle, WA
from March 1-5, 2008. ASPLOS is a multi-disciplinary conference for research that spans the boundaries of hardware,
computer architecture, compilers, languages, operating systems, networking, and applications. ASPLOS provides a high
quality forum for scientists and engineers to present their latest research findings in these rapidly changing fields.
It has captured some of the major computer systems innovations of the past two decades (e.g., RISC and VLIW processors,
small and large-scale multiprocessors, clusters and networks-of-workstations, optimizing compilers, RAID, and network-
storage system designs). This conference occurs at a time when computer architecture is facing great challenges, due both
to the end of single-processor performance scaling and to new demands imposed by mobile and gigascale computing.
In addition to the main program, this upcoming ASPLOS will offer several tutorials and workshops on a variety of
focus areas.
Abstract Deadline:
August 1, 2007 (11pm Pacific Daylight Savings Time)
Full Paper Deadline:
August 7, 2007(11pm Pacific Daylight Savings Time)
Rebuttal Period:
October 11-12, 2007
Notification of Acceptance:
November 1, 2007
Final Paper Submission:
December 31, 2007
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* IISWC 2007 Call for Benchmarks: The Annual 2007 IEEE International Symposium on Workload Characterization
2007 IEEE International Symposium on Workload Characterization
IISWC 2007
September 27-29 2007,
Boston, MA, USA
Web site: http://www.iiswc.org
This symposium is dedicated to the understanding and
characterization of workloads which run on all types
of computer systems. New applications and programming
paradigms continue to emerge as the use of computers
becomes more widespread and more sophisticated. Improving
process and communication technology, innovations in microarchitecture,
compilers, and virtual machine technology are also changing the
nature of problems that are being solved by computing systems.
Whether they are PDAs, wireless and embedded systems at the low end or
massively parallel systems at the high end, the design of tomorrow's
computing machines can be significantly improved through the
knowledge and ability to simulate the workload expected to run on them.
Important dates
---------------
Abstract submission: March 12, 2007
Paper submissions: March 19, 2007
Acceptance Notification: May 28, 2007
Topics of Interest
------------------
Papers are solicited in all areas related to characterization of
computing system workload. Topics of interest to participants in
the symposium include (but are not limited to):
* Characterization of applications in areas like
o Search engines, E-commerce, Web server, Database, and
Multi-tier applications
o Embedded, Mobile, Multimedia, 3d-Graphics, Gaming,
Telepresence
o Life Sciences, Bio-informatics, Scientific Computing
o Security, Reliability, Biometrics
* Characterization of OS, Virtual Machines, Middleware and Library Behavior
o VMs, Websphere, .NET, Java VM, CLI
o Graphics libraries, scientific libraries
* Characterization of system behavior, including
o Operating system and hypervisor effects
o Effects due to virtualization and dynamic optimization
o Failures, availability, and reliability
* Implications of workload in design issues, such as
o Processors, memory hierarchy, I/O, and networks
o Hardware accelerators (GPGPU, XML, crypto, etc.)
o Power management, reliability, security
* Benchmark creation issues, including
o Multithreaded benchmarks
o Profiling, trace collection, synthetic traces
o Validation of benchmarks
* Abstract modeling of program behavior
Submission format
Submissions need to be in 2-column IEEE Proceedings style format with a limit of 10 pages including figures, references, etc.
The text font sizes should be no smaller than 10pt with single spacing. Submissions need to be in PDF format that should be
readable with Adobe Acrobat Reader. Accepted papers will be published as an IEEE Proceedings.
COMMITTEES
General Chair
-------------
Mauricio Breternitz, Intel
Program Chairs
--------------
Anand Sivasubramaniam, Penn State University
David Christie, AMD
Workshop/Tutorials Chair
------------------------
Wei W. Liu, Intel
Web and Publicity Chair
-----------------------
Bhuvan Urgaonkar, Penn State University
Local Arrangements Chair
------------------------
Resit Sendag, University of Rhode Island
Program Committee
-----------------
Carole Dulong, Google
Lieven Eeckhout, Ghent Univ.
Michael Gschwind, IBM
Sudhanva Gurumurthi, Univ. of Virginia
Ravi Iyer, Intel
John Janakiraman, HP Labs
Kevin Lepak, AMD
Tao Li, Univ. of Florida
David Lilja, Univ. of Minnesotta
Gokhan Memik, Northwestern Univ.
Chuck Moore, AMD
Ramesh Peri, Intel
Alma Riska, Seagate
Yan Solihin, NC State Univ.
Rajeev Thakur, Argonne Natl. Lab.
Jeff Vetter, Oak Ridge
Murali Vilayannur, VMWare
Joshua Yi, Freescale
Steering Committee
------------------
Pradip Bose, IBM Research
Tom Conte, NC State University
Lieven Eeckhout, Ghent University
Jay Jayasimha, Intel
Lizy John, University of Texas at Austin
David Kaeli, Northeastern University
David Lilja, University of Minnesota
Ann Marie Maynard, IBM
Ravi Nair, IBM
John Shen, Nokia
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* ISPASS-2007 Call for Participation: International Symposium on Performance
Analysis of Systems and Software
==== CALL FOR PARTICIPATION ====
ISPASS-2007
International Symposium on Performance
Analysis of Systems and Software
April 25-27, 2007
Hilton San Jose
San Jose, California, USA
http://www.ispass.org
The 2007 IEEE International Symposium on Performance Analysis of Systems and Software is sponsored by the IEEE Computer
Society's Technical Committee on Internet, Technical Committee on Computer Architecture, and Technical Committee on
Microprogramming and Microarchitecture.
The advanced program is now available, and the registration website is open. Early registration ends April 16th, 2007.
Special rate on theconference hotel must be booked by April 4th. Please visit http://www.ispass.org for more information
and registration.
[Advanced Program]
Keynote I: Don Newell, Intel Corporation, "Workloads, Scalability, and QoS Considerations in CMP Platforms"
Keynote II: Leslie Barnes, AMD Corporation, "Performance Modeling and Analysis for AMD's High Performance Microprocessors"
Session 1: Simulators/Simulation Methodology
* Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance; Seongbeom Kim,
Fang Liu, and Yan Solihin (North Carolina State University), Ravi Iyer and Li Zhao (Intel Corporation), and
William Cohen (Red Hat)
* A Comparison of Two Approaches to Parallel Simulation of Multiprocessors; Andrew Over, Peter Strazdins,
and Bill Clarke (Australian National University)
* PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator; Matt T. Yourst (State University of New York
at Binghamton)
Session 2: Application Characterization
* Memory Performance of Data-Mining Workloads on Small-, Medium-, and Large-Scale CMPs; Wenlong Li, Eric Li, Jiulong Shan,
Yurong Chen, Aamer Jaleel, Qigang Wang, Ravi Iyer, Ramesh Illikkal, Yimin Zhang, and Dong Liu (Intel Corporation)
* Characterizing a Complex J2EE Workload: A Comprehensive Analysis and Opportunities for Optimizations; Yefim Shuf
(IBM T.J. Watson Research Center), and Ian M. Steiner (Intel Corporation)
* Performance Characterization of Decimal Arithmetic in Commercial Java Workloads; Mahesh Bhat, John Crawford,
Ricardo Morin, and Kumar Shiv (Intel Corporation)
* Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video CODEC Applications; Mauricio Alvarez,
Esther Salam, Alex Ramirez, and Mateo Valero (Universitat Politecnica de Catalunya)
Session 3A: Simulation Sampling I
* Combining Simulation and Virtualization through Dynamic Sampling; Ayose Falcon, Paolo Faraboschi, and Daniel Ortega
(HP Labs)
* Phase-Guided Small Sample Simulation; Joshua Kihm, Samuel Strom, and Daniel A. Connors (University of Colorado)
Session 3B: Prefetching
* DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance, and Power Saving; Jiang Lin (Iowa State University),
Hongzhong Zheng (University of Illinois at Chicago), Zhao Zhang (Iowa State University), Zhichun Zhu (University of
Illinois at Chicago), and Howard David (Intel Corporation)
* Last-Touch Correlated Data Streaming; Michael Ferdman and Babak Falsafi (Carnegie Mellon University)
Session 4: Performance Models and Phase Classification
* Using Model Trees for Computer Architecture Performance Analysis of Software Applications; ElMoustapha Ould-Ahmed-Vall,
James Woodlee, Charles Yount, Kshitij A. Doshi, and Seth Abraham (Intel Corporation)
* Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility; Xudong Shi, Feiqi Su, Jih-Kwon Peir,
Ye Xia, and Zhen Yang (University of Florida)
* Using Wavelet Domain Workload Execution Characteristics to Improve Accuracy, Scalability, and Robustness in Program
Phase Analysis; Chang-Burm Cho and Tao Li (University of Florida)
Session 5A: Power and Reliability
* Modeling and Characterizing Power Variability in Multicore Architectures; Ke Meng, Frank Huebbers, Russ Joseph, and
Yehea Ismail (Northwestern University)
* Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events; William Lloyd Bircher and
Lizy Kurian John (University of Texas at Austin)
* An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures; Wangyuan Zhang,
Xin Fu, Tao Li, and Jose Fortes (University of Florida)
Session 5B: Simulation Sampling and Performance Prediction
* Cross Binary Simulation Points; Erez Perelman and Jeremy Lau (University of California at San Diego), Harish Patil and
Aamer Jaleel (Intel Corporation), Greg Hamerly (Baylor), and Brad Calder (UC San Diego and Microsoft)
* Reverse State Reconstruction for Sampled Microarchitectural Simulation; Paul D. Bryan, Michael C. Rosier, and Thomas M.
Conte (North Carolina State University)
* An Analysis of Performance Interference Effects in Virtual Environments; Younggyun Koh (Intel Corporation and
Georgia Institute of Technology), Rob Knauerhase, Paul Brett, Mic Bowman (Intel Corporation), Zhihua Wen (Intel
Corporation and Case Western Reserve University), and Calton Pu (Georgia Institute of Technology)
Session 6A: Evaluating Real Systems
* Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications; Daniel Jimenez-Gonzalez,
Xavier Martorell, and Alex Ramirez (UPC-DAC, BSC)
* Benefits of I/O Acceleration Technology (I/OAT) in Clusters; Karthikeyan Vaidyanathan and D. K. Panda (Ohio State
University)
Session 6B: Memory Systems
* CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications; Sangyeun Cho, Joel R. Martin, Ruibin Xu,
Mohammad H. Hammoud, and Rami Melhem (University of Pittsburgh)
* Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads; Dhiraj D. Kalamkar (Intel Corporation,
Bangalore), Mainak Chaudhuri (Indian Institute of Technology, Kanpur), and Mark Heinrich (University of Central Florida)
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* WDDD 2007 Call for Papers: Workshop on Duplicating, Deconstructing, and Debunking
*************************************************************
CALL FOR PAPERS: WDDD 2007
*************************************************************
Workshop on Duplicating, Deconstructing, and Debunking
http://www.ece.wisc.edu/~wddd
Held in conjunction with ISCA-34
San Diego, California USA
June 10, 2007
-------------------------------------------------------------
IMPORTANT DATES
---------------
Abstracts due: April 16
Submissions due: April 24
Acceptance: May 4
Final version: May 11
WORKSHOP OVERVIEW
-----------------
WDDD provides the computer systems research community a forum
for work that validates or duplicates earlier results; deconstructs
prior findings by providing greater, in-depth insight into causal
relationships or correlations; or debunks earlier findings by
describing precisely how and why proposed techniques fail where earlier
successes were claimed, or succeed where failure was reported.
Traditionally, computer systems conferences and workshops focus
almost exclusively on novelty and performance, neglecting an abundance
of interesting work that lacks one or both of these attributes. A
significant part of research--in fact, the backbone of the scientific
method--involves independent validation of existing work and the
exploration of strange ideas that never pan out. This workshop
provides a venue for disseminating such work in our community.
Published validation experiments strengthen existing work, while
thorough comparisons provide new dimensions and perspectives.
Studies that refute or correct existing work also strengthen the
research community, by ensuring that published material is technically
correct and has sound assumptions. Publishing negative or strange or
unexpected results will allow future researchers to learn the
hard lessons of others, without repeating their effort.
This workshop will set a high scientific standard for such
experiments, and will require insightful analysis to justify
all conclusions. The workshop will favor submissions that
provide meaningful insights and point to underlying root causes
for the failure or success of the technique under investigation.
Acceptable work must thoroughly investigate and clearly communicate
why the proposed technique performs as the results indicate.
Rebuttals may be invited for debunking submissions.
SUBMISSION TOPICS
-----------------
* Independent validation of earlier results with meaningful analysis
* In-depth analysis and sensitivity studies that provide further
insight into earlier findings, or identify key parameters or
assumptions that affect the results
* Studies that refute earlier findings, with clear justification
and explanation
* Negative results for ideas that intuitively make sense and
should work, along with explanations for why they do not
WORKSHOP SCOPE
--------------
Computer Architecture
* Processor architecture/microarchitecture
* Memory hierarchy
* Multiprocessor systems
* Power-efficient architectures
* Dependable architectures
* Compiler/architecture interaction
* Application-specific, reconfigurable, and embedded architectures
Code generation and Optimization
* Feedback-driven optimization
* Phase-based optimization
* Dynamic compilation, adaptive/continuous optimization
* Modulo/trace scheduling
* Efficient profiling techniques
* Binary translation/optimization
* Parallel compilation/compiler support for thread level speculation
SUBMISSION GUIDELINES
---------------------
* Submit a 200-word abstract plus title and list of authors in
plain text email by April 16 to tcain@xxxxxxxxxxx
* Submit a 5000-word or less (brief and to-the-point submissions
are strongly encouraged) double-spaced manuscript by April 14
as a PS or PDF file on the workshop website www.ece.wisc.edu/~wddd
Inappropriate submissions, as described in the submitted abstract,
will be rejected outright. Similarly, inflammatory, abusive, or
overtly combative and negative submissions will not be considered.
Accepted papers will be published in the ISCA-34 workshop proceedings.
WORKSHOP ORGANIZERS
-------------------
Bryan Black, bryan.black@xxxxxxxxx
Harold Cain, IBM Research, tcain@xxxxxxxxxx
PROGRAM COMMITTEE
-----------------
David August, Princeton
Bryan Black, Intel Labs
Mauricio Breternitz, Intel
Harold Cain, IBM Research
Rich Hankins, Nokia
Mike Hind, IBM Research
Stephen Keckler, University of Texas-Austin
Mikko Lipasti, University of Wisconsin-Madison
Gabriel Loh, Georgia Tech
Ryan Rakvic, US Naval Academy
Eric Rotenberg, NC State University
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* MoBS 2007 Call for Papers: Workshop on Modeling, Benchmarking, and Simulation
********************************************************************************
* *
* Call for Papers and Tools *
* *
* MoBS: Workshop on Modeling, Benchmarking, and Simulation *
* http://www.arctic.umn.edu/~jjyi/MoBS *
* *
********************************************************************************
Held in conjunction with the 34th Annual International Symposium on Computer Architecture
San Diego, California
June 10, 2007
Overview:
=========
With few exceptions, simulation is the quantitative foundation for virtually all computer architecture research and
design projects ? from microarchitectural exploration to hardware and software trade-offs to processor and system design.
However, its continued efficacy is limited by the need to model or compensate for problems such as increasing complexity
(e.g., multiple cores), additional critical design constraints (e.g., power consumption, reliability, etc.), an ever
expanding design space, and benchmark suite quality and coverage.
Accordingly, the goals of this workshop are to accelerate the development of technologies that are necessary to support
the research and development of future generation architectures and to encourage the advancement of ?under-researched?
areas in computer architecture measurement. Consequently, this workshop places a special premium on novelty and on
preliminary work. Topics of interest include, but are not limited to:
* Performance/energy/temperature measurement and analysis tools
* New or efficient techniques to model performance, power, temperature, reliability, etc.
* Simulation methodologies for multi-core architectures
* Development of parameterizable, flexible benchmarks
* Efficient processor modeling techniques
* Alternatives to cycle-accurate, execution-driven simulation
* Statistically-rigorous performance analysis techniques
* Analytical and statistical modeling
==============================================================
Special session on Measurement and Performance Analysis Tools:
==============================================================
This workshop will feature a special session on measurement and performance analysis tools. All submissions to this
session must include a paper describing the tool, examples of how the tool could be used, and its source code.
Submissions will be judged based on their novelty and ease of installation/use. The presentations for accepted
submissions will consist of an overview of the tool (15 minutes) followed by a demonstration of its capabilities
(15 minutes). Open-source versions of all tools will be released before or by the end of the workshop.
Submission Guidelines:
======================
The authors should submit a 200 word or less abstract by 11:59 PM April 2, 2007. The full paper should be 5000 words or
less and be submitted in pdf format by 11:59 PM April 6, 2007. Both the abstract and the full paper can be submitted to
Lieven Eeckhout (leeckhou@xxxxxxxxxxxxx) through email. Papers can be submitted as a regular paper or tool. Excessively
long papers may be rejected without review.
Important Dates:
================
Abstract Submission: April 2, 2007
Full Paper Submission: April 6, 2007
Notification Date: May 4, 2007
Final Version Due: May 18, 2007
Workshop Date: June 10, 2007
Co-Organizers and Program Co-Chairs:
====================================
Lieven Eeckhout, Ghent University (leeckhou@xxxxxxxxxxxxx)
Joshua J. Yi, Freescale Semiconductor (jjyi@xxxxxxxxxxx)
Program Committee:
==================
David Brooks, Harvard University
Derek Chiou, UT-Austin
Joel Emer, Intel
Babak Falsafi, Carnegie Mellon University
Russ Joseph, Northwestern University
Tejas Karkhanis, AMD
Sally McKee, Cornell University
Harish Patil, Intel
Steve Reinhardt, Reservoir Labs / U of Michigan
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* TRIPS Toolchain Released for Research Use
* TRIPS Tools Released
The TRIPS team at UT-Austin has released a suite of tools for
researchers to use.The tools include a C and FORTRAN compiler that
generates TRIPS ISA binaries, functional and timing simulators,
a full binary toolchain, and performance analysis tools.
The tools have been validated against and tested on working hardware,
and are fairly stable. Currently, they are only supported on x86/Linux
platforms.
Access to the tools may be obtained by filling out the form at:
http://www.cs.utexas.edu/~trips/ttools-req
The tools are intended for research purposes only.
For a commercial license, please contact the maintainers at cart@xxxxxxxxxxxxxx
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* Power.org DevCon 07 Call for Papers: Power Architecture Developer Conference 2007
Power.org is hosting a developers conference in Austin TX in September
that includes a refereed paper track for publications that
use/enhance/extend Power Architecture Systems.
http://www.power.org/devcon/07/callforpapers/
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* CRA-W/CDC Programming Languages Summer School Workshop
********************************************************
CRA-W/CDC Programming Languages Summer School Workshop
May 9-11, 2007
The University of Austin, TX
********************************************************
http://www.cs.utexas.edu/users/mckinley/pl-summer-2007/
Please spread the word about this new program!
Application deadline March 22nd!
********************************************************
As a joint effort of the Computing Research Association's Committee on the Status of Women (CRA-W) and the Coalition to
Diversify Computing (CDC), we are organizing a summer school workshop in Programming Languages to be held at the University
of Texas at Austin on May 9-11, 2007. The workshop is particularly targeted at women and under-represented minority graduate
students and early-career faculty with research interests in programming languages. Through technical panel sessions with
academic and industry leaders, as well as other informal activities, the summer school will provide mentoring for these
students and faculty as they get started with their careers. A webpage with basic information and the application form is
now available at: http://www.cs.utexas.edu/users/mckinley/pl-summer-2007/.
Our effort is inspired and modeled on last year's well received Computer Architecture Summer School held at Princeton,
also sponsored by CRA-W and CDC (http://www.princeton.edu/~archss06/). CRA-W and CDC plan additional area specific workshops
with a technical focus. Call for proposals can be found here: http://www.cra.org/Activities/craw/cdc/.
Via funding from NSF's Broadening Participation in Computing (BPC) program, we will provide reasonable travel support for
students. There is no charge for the summer school.
Feel free to email questions to the workshop organizers, Kathryn McKinley (mckinley@xxxxxxxxxxxxx) and Daniel A. Jimenez
(dj@xxxxxxxxxxx), for more information.
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