[Sigarch-members] SIGARCH-MSG: 2nd June 2007 Digest of SIGARCH Messages

["Doug Burger" <dburger@xxxxxxxxxxxxx>]

This is the 2nd June 2007 Digest of SIGARCH Messages (sigarch-june07b):

* ASPLOS 2008 Call for Workshops and Tutorials: ASPLOS XIII (13th International Conference on Architectural Support for Programming Languages and Operating Systems), Seattle, WA
  http://research.microsoft.com/asplos08/
  Submitted by Onur Mutlu <onur@xxxxxxxxxxxxx>

* Hot Chips 2007 Call for Participation: Hot Chips 2007, August 19-21, 2007, Stanford University; Palo Alto, California
  http://www.hotchips.org
  Submitted by Alan Smith <smith@xxxxxxxxxxxxxxxxx>

--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@xxxxxxx

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Doug Burger			  Office:	       3.432 ACES
Associate Professor		  Phone:	     512-471-9795
Department of Computer Sciences	  Assistant:	     512-232-7460
The University of Texas at Austin Fax:		     512-232-1413
1 University Station, #C0500	  E-mail:   dburger@xxxxxxxxxxxxx
Austin, TX 78712-1188 USA	  www.cs.utexas.edu/users/dburger
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* ASPLOS 2008 Call for Workshops and Tutorials: ASPLOS XIII (13th International Conference on Architectural Support for Programming Languages and Operating Systems), Seattle, WA
  http://research.microsoft.com/asplos08/

CALL FOR WORKSHOPS and TUTORIALS

ASPLOS XIII (13th International Conference on Architectural Support for Programming Languages
and Operating Systems), Seattle, WA


March 1 - 5, 2008


http://research.microsoft.com/asplos08/


ASPLOS is a multi-disciplinary conference for research that spans the boundaries of hardware,
computer architecture, compilers, languages, operating systems, networking, and applications.
ASPLOS provides a high quality forum for scientists and engineers to present their latest 
research findings in these rapidly changing fields. It has captured some of the major 
computer systems innovations of the past two decades (e.g., RISC and VLIW processors, small 
and large-scale multiprocessors, clusters and networks-of-workstations, optimizing compilers, 
RAID, and network-storage system designs).

Call for Workshops
Proposals are solicited for workshops to be organized in conjunction with ASPLOS-XIII. 
Please keep in mind that the goal of workshops is to foster discussion on new topics in 
emerging areas. Also, that a major characteristic of the workshops should be high level 
of interactivity.

Please choose the workshop topics and format accordingly. Send your workshop proposals to 
Mike Swift (_swift@xxxxxxxxxxxx) before October 1, 2007, with the following information:

   1. Title of the workshop
   2. Organizers and their affiliations
   3. A sample call for papers, including workshop's main objectives, main topics, and 
      expected program committee (if possible)
   4. Expected duration of the workshop; i.e., 1/2 day, full day, or 2 days
   5. Expected workshop fomat. I.e., keynote+talks+panel, keynote+talks, etc. Also, for 
      talks, what is the expected breakdown for presentation and questions. 
      E.g., for a 30 minute talk, 25+5, or 20+10, etc
   6. If the workshop was previously held, the number of published papers and attendees 
      at the last workshop
   7. Please answer the following two questions pointedly (not as a part of the sample 
      call for papers):
          * How/why would the workshop be useful to the ASPLOS community?
          * What specific plans do you have to make the workshop interactive?

Call for Tutorials
Proposals are solicited for tutorials to be organized in conjunction with ASPLOS-XIII. 
Please keep in mind that the goal of tutorials is to educate the community on a new idea, 
practice, or tool. Also, that a major characteristic of the tutorials should be high level 
of interactivity. Please choose the tutorial topics and format accordingly.

Please send your tutorial proposals to Mike Swift (_swift@xxxxxxxxxxxx) before 
October 1, 2007, with the following information:


   1. Title of the tutorial
   2. Organizers, presenters, and their affiliations
   3. Description of the main objectives of the tutorial, topics covered (and some related 
      bibliography ), the target audience, and prerequisite knowledge.
   4. Expected duration of the tutorial; i.e., 1/2 day, full day, or 2 days
   5. Expected tutorial format. I.e., talks, or talks + demo, etc.
   6. If the tutorial was previously held, the location (i.e., which conference), date, 
      and number of attendees at the last tutorial
   7. Please answer the following two questions pointedly:
          * How/why would the tutorial be useful to the ASPLOS community?
          * What specific plans do you have to make the tutorial interactive?

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* Hot Chips 2007 Call for Participation: Hot Chips 2007, August 19-21, 2007
  Stanford University; Palo Alto, California

		      HOT Chips 19 ADVANCE PROGRAM

                   A Symposium on High-Performance Chips
                 August 19-21, 2006, Memorial Auditorium,
                Stanford University, Palo Alto, California   


HOT Chips brings together designers and architects of high-performance
chips, software, and systems. Presentations focus on up-to-the-minute
real developments. This symposium is the primary forum for engineers and
researchers to highlight their leading-edge designs.  Three full days of
tutorials and technical sessions will keep you on top of the industry.


See  http://www.hotchips.org  for registration information, local
arrangements, location, etc.


            ------------------------------------------------
                         Sunday, August 19, 2007
            ------------------------------------------------


Morning Tutorial:
 Approaches to System Design for the Working Engineer
  Part 1 ASICs and ASSPs - David Witt (Texas Instruments)
  Part 2 FPGAs, from Glue Logic to Systems Components: Twenty Years of FPGA Evolution 
         - Peter Alfke (Xilinx) 
  Part 3 Exploiting Chip-Level Processor Heterogeneity through Fine-Grained Reconfigurable 
         Interactions
         - Shephard Siegel (Mercury Computer Systems)

Lunch

Afternoon Tutorial
 Enterprise Power and Cooling: A Chip-to-Data Center Perspective
   Chandrakant Patel           (HP Labs)
   Parthasarathy Ranganathan   (HP Labs)
     Part I: Background
     Part II: Cooling: A Chip-core to Cooling-Tower Perspective
     Part III: Power: From Chips to Data Centers
     Part IV: Case Study and Future Directions




      ------------------------------------------------
                   Monday, August 20, 2007
      ------------------------------------------------

Opening Remarks

IBM Power6
       * Fault-Tolerant Design of the IBM POWER6 Microprocessor (IBM) 
       * System Performance Scaling of IBM POWER6 Based Servers (IBM) 
       * The Third Generation of IBM's Elastic Interface (EI-3) Implementation on  
         POWER6(TM) (IBM)  

Keynote 1:   Vernor Vinge, computer scientist and science fiction writer who has novelized potential interactions between machines and humans, author of True Names and Rainbows End. 

Lunch

Multi-core & Parallelism A
       * NVIDIA GeForce 8800 GPU (NVIDIA)
       * The NVIDIA GPU Parallel Computing Architecture (NVIDIA)
       * Performance Insights of Executing Non-Graphics Applications on the NVIDIA 
         GeForce 8800(TM) and the CUDA(TM) Parallel Programming Environment (UIUC)

Multi-core & Parallelism B       
       * Radeon R600 Technology, a 2nd Generation Unified Shader Architecture (AMD)
       * Teraflop Prototype Processor with 80 Cores (Intel)
       * Design and Implementation of the TRIPS Prototype Chip (UT Austin)
       * The Tile Processor: Embedded Multicore for Networking and Digital Multimedia 
         (Tilera Corporation)  

Embedded and Video 
       * SH-X3: Flexible SuperH Multi-Core for High-Performance and Low-Power Embedded  
         Systems (Renesas) 
       * An Innovative HD Video and Digital Image Processor for Low-Cost Digital 
         Entertainment Products (Texas Instruments) 
       * Professional H.264/AVC CODEC Chip-Set for High-Quality HDTV Broadcast 
         Infrastructure and High-End Flexible CODEC Systems (NTT)  

Dinner

Panel: What's next beyond CMOS?
        Chair: Norm Jouppi (Hewlett Packard)
        Panelists:
          Mark Horowitz (Stanford University)
          John Kubiatowicz (UC Berkeley)
          Mike Mayberry (Intel)
          Ghavam Shahidi (IBM) 
          Stan Williams (Hewlett Packard)

      ------------------------------------------------
             Tuesday, August 21, 2007
      ------------------------------------------------   


Technology and Software Directions 


       * Multiterabit Switch Fabrics Enabled by Proximity Communication (Sun) Memory 
         Technology for Nano-Scale CMOS   (T-RAM Semiconductor) 
       * Raksha: A Flexible Architecture for Software Security (Stanford) 


Wireless 
       * A 4 Gbps Wireless Uncompressed 1080p-Capable HD A/V Transceiver using 60 GHz 
         (SiBeam)  
       * A 2x2 MIMO Baseband for High-Throughput Wireless Local-Area Networking (802.11n) 
         (Broadcom) 

Keynote 2:  
       *  Multicore and Beyond: Evolving the X86 Architecture 
          Phil Hester (CTO AMD)

Lunch

Networking 
       * A Packet Processing Chip Set (Cisco) 
       * Chesapeake: A 50Gbps Combined Network Processor and Traffic Manager 
         (Bay Microsystems)   
       * A System on a Chip with Integrated Accelerators (Intel) 
       * Focalpoint II, A Low-Latency, High Bandwidth Switch/Router Chip
         (Fulcrum Microsystems)   

Mobile PC Processors and Chipsets  
       * Advanced Power Management Features in Penryn - 45nm Next Generation Intel Core(TM)2 
         Duo Microarchitecture (Intel)  
       * Next Generation Mobile X86 Processor (AMD) 
       * nForce 680i and 680, NVIDIA's Next Generation Platform Processors 
         (NVIDIA)  


Big Iron 
       * VictoriaFalls - Scaling Highly-Threaded Processor Cores (Sun) 
       * The Next-Generation Mainframe Microprocessor (IBM) 


Special Presentation
       * "Wireless Broadband and Entrepreneurship in America" Reed Hundt
         (Frontline Wireless.  Former chair FCC)

This is a preliminary program; changes may occur.   For the most up-to-the-minute details 
on presentations and schedules,  and for registration information, please visit our web 
site where you can also check out HOT Interconnects (another HOT Symposium being held 
following HOT Chips): 


                 Website:        http://www.hotchips.org  
                  Email:          info2007@xxxxxxxxxxxx  

Registration: 
Early Registration:       June 1, 2007 to July 31, 2007 

                   Tutorials Only     Conference Only      Both 
ACM/IEEE Members      $100                  $295           $395 
Non-Members           $125                  $395           $520 
Student Members       $85                   $85            $170 
Student Non-Members   $90                   $110           $200 

Late Registration:       After July 31st, 2007  

                   Tutorials Only     Conference Only      Both 
ACM/IEEE Members      $175                  $475           $650 
Non-Members           $200                  $575           $775 
Student Members       $95                   $145           $240 
Student Non-Members   $100                  $150           $250 


Registration fees for Tutorials include a printed set of tutorial notes, 
continental breakfast, lunch, coffee break, and invitation to the evening 
Wine and Cheese Reception on Sunday, August 19, 2007.

Registration fees for the Conference include a flash drive containing a 
set of the conference proceedings (printed sets are available for 
purchase with advance registration), Monday night dinner, continental 
breakfasts, lunches and coffee breaks during the two days 
(August 20-21, 2007) of the conference. It also includes an invitation to 
the evening Wine and Cheese Reception on Sunday, August 19, 2007.

Organizing Committee:
       General Chair:          John Sell          Microsoft
       Vice Chair:             Don Draper         Rambus
       Finance:                Lily Jow           HP
       Publicity:              Kevin Krewell      NVIDIA
                               Gail Sachs         Telairity
       Advertising:            Don Draper         Rambus
       Sponsorship:            Amr Zaky           Broadcom
       Publications:           Gordon Garb        Sun
       Registration:           Ravi Rajamani      Oracle
                               Sujata Ramasubramanian  Intel
       Local Arrangements:     Lance Hammond      Apple
       Webmaster:              Alexis Cordova  


Steering Committee:    
           Don Alpert              Camelback Arch.
           Allen Baum              Intel
           Pradeep Dubey           Intel   
           Lily Jow                HP
           John Mashey             Techviser  
           Howard Sachs            Telairity
           Alan Jay Smith          UC Berkeley  

Program Committee Co-Chairs:
           Rajeevan Amirtharajah   UC Davis  
           John Mashey             Techviser

Program Committee:
           Forrest Baskett          NEA
           Dileep Bhandarkar        Microsoft
           Doug Burger              UT Austin  
           Christos Kozyrakis       Stanford
           Norm Jouppi              HP Labs
           John Montrym             NVIDIA 
           Chuck Moore              AMD
           Mitsuo Saito             Toshiba
           Alan Jay Smith           UC Berkeley
           Marc Tremblay            Sun Micro
           Jan-Willem van de Waerdt NXP Semiconductors
           Ralph Wittig             Xilinx

Founder:   Bob Stewart              SRE 

Hot Chips is A Symposium of the Technical Committee on Microprocessors
and Microcomputers of the IEEE Computer Society and the IEEE Solid
State Circuits Society