This is the 1st March 2007 Digest of SIGARCH Messages (sigarch-mar07a):
* HOTCHIPS 19 Call for Papers
http://www.hotchips.org
Submitted by Alan Smith <smith@xxxxxxxxxxxxxxxxx>
* Final Report Available: 2005 CRA Conference on Grand Research Challenges
http://www.cra.org/Activities/grand.challenges/architecture/home.html
Submitted by Mary Jane Irwin <mji@xxxxxxxxxxx>
* SC07 Call for Papers: 20th International Conference for High-Performance Computing, Networking, Storage and Analysis
http://sc07.supercomputing.org/
Submitted by Josep Torrellas <torrellas@xxxxxxxxxxx>
* WIOSCA 2007 Call for Papers: Workshop on the Interaction between Operating Systems
and Computer Architecture
http://www.ideal.ece.ufl.edu/wiosca
Submitted by James M. Poe II <jpoe@xxxxxxx>
* COOL Chips X Call for Posters: IEEE Symposium on Low-Power and High-Speed Chips
http://www.coolchips.org/
Submitted by Toshi Sato <tsato@xxxxxxxxxxxxxxxxxxx>
* ACACES 2007 Call for Participation: Third International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
http://www.hipeac.net/summerschool
Submitted by Koen De Bosschere <Koen.DeBosschere@xxxxxxxxxxxxx>
* WCAE 2007 Call for Papers: Workshop on Computer Architecture Education, held in conjunction with ISCA-34
http://www4.ncsu.edu/~efg/wcae2007.html
Submitted by Ed Gehringer <efg@xxxxxxxx>
* TRANSACT '07 Call for Papers: The Second ACM SIGPLAN Workshop on Transactional Computing
http://www.cs.rochester.edu/meetings/TRANSACT07/
Michael L Scott <scott@xxxxxxxxxxxxxxxx>
* IISWC 2007 Call for Benchmarks: The Annual 2007 IEEE International Symposium on Workload Chacterization
http://www.iiswc.org/
Submitted by Lieven Eeckhout <lieven.eeckhout@xxxxxxxx>
* PACT '07 Call for Papers: 16th International Conference on Parallel Architectures and Compilation Techniques
http://pactconf.org
Submitted by Silvius Rus <rus@xxxxxxxxxx>
* Call for Papers Special Issue: Circuits and Systems for Real-Time Security and
Copyright Protection of Multimedia
International Journal of Computers and Electrical Engineering (Elsevier Ltd.)
http://www.elsevier.com/wps/find/journaldescription.cws_home/367/description
Submitted by Saraju P. Mohanty <sarajumohanty@xxxxxxxxx>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@xxxxxxx
* Archive: http://lists.cs.wisc.edu/archive/sigarch-members/
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@xxxxxxx with message body: unsubscribe SIGARCH-MEMBERS
-----------------------------------------------------------------
Doug Burger Office: 3.432 ACES
Associate Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
The University of Texas at Austin Fax: 512-232-1413
1 University Station, #C0500 E-mail: dburger@xxxxxxxxxxxxx
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* HOTCHIPS 19 Call for Papers: A Symposium on High-Performance Chips (HOTCHIPS - 2007)
A Symposium on High-Performance Chips - HOT CHIPS 19 -
Stanford University, Palo Alto, California
August 19-21, 2007(tentative)
AUTHOR'S SCHEDULE
Deadline for submissions: March 25, 2007
Notification of acceptance: April 30, 2007
Deadline for final version: July 13, 2007
AREAS OF INTEREST:
- Microprocessors - Novel chips: quantum computing,
- Systems-on-chip nano-structures, micro-arrays
- Embedded processors - Low-power chips/Dynamic power management
- Chipset chips - Graphics/Multimedia/Game processors/
- Digital signal processors Display technology
- Application-specific processors - Advanced semiconductor process technology
- Communication/networking chips - Reconfigurable chips/processors
- Wireless LAN/Wireless WAN chips - Operating system/chip interaction
- Network/security processors - Advanced packaging technology
- Chips built from FPGAs - Reliability and design for test
- Compiler technology - Performance evaluation
AUTHOR INFORMATION AND FORMAT
Presentations at HOT Chips are in the form of 30-minute talks. Presentation slides will be
published in the HOT Chips Proceedings. Participants are not required to submit written
papers, but a select group will be invited to submit a paper for inclusion in a special
issue of IEEE Micro.
Submissions must consist of a title, extended abstract (two pages maximum.), and the
presenter's contact information (name, affiliation, job title, address, phone(s), fax,
and email). Please indicate whether you have submitted, intend to submit, or have already
presented or published a similar or overlapping submissionto another conference or journal. Also indicate if you would like the submission to be held
confidential; we do our best to maintain confidentiality if requested.
Submissions should be in plain ASCII text, pasted into the message; do not submit .doc
files, .txt files, MIME'd email, any attachments or other formats. Submissions containing
figures may be submitted in pdf, but plain ASCII text is strongly preferred.
Submissions are evaluated by the Program Committee on the basis of performance of the
device(s), degree of innovation, use of advanced technology, potential market significance,
and anticipated interest to the audience. Research and software contributions will be
evaluated with similar criteria.
Please mail your submissions in plain ASCII text (in the message, not as an attachment!) by
March 25, 2007 to: submit2007@xxxxxxxxxxxx Authors will be notified as to acceptance by
April 30, 2007. Send questions relating to the program to the program chairs at:
program2007@xxxxxxxxxxxx and questions relating to conference operation or organization to
the general chair, John Sell, at: info2007@xxxxxxxxxxxx .
Program Committee Co-Chairs:
John Mashey, Techviser
Raj Amirtharajah, UC Davis
Sponsored by the Technical Committee on Microprocessors and Microcomputers of the
IEEE Computer Society.
Check the HOT CHIPS 19 web page for updates: http://www.hotchips.org
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* Final Report Available: 2005 CRA Conference on Grand Research Challenges
Final report from the 2005 CRA Conference on Grand Research Challenges: Revitalizing
Computer Architecture Research is now available on line at
http://www.cra.org/Activities/grand.challenges/architecture/home.html
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* SC07 Call for Papers: 20th International Conference for High-Performance
Computing, Networking, Storage and Analysis
==============================================================
CALL FOR PAPERS
SC07
20th International Conference for High-Performance
Computing, Networking, Storage and Analysis
Reno, Nevada November 12-16, 2007
http://sc07.supercomputing.org/
Sponsors: ACM SIGARCH/IEEE Computer Society
==============================================================
SC07, the premier international conference on high-performance
computing, networking, storage and analysis, provides a forum of
the highest quality for scientists and engineers to present their
latest research findings in one of most rapidly changing technical
fields. We invite you to submit your work on all aspects of
architecture, applications, performance, system software, networks,
and grids. Topics of interest include, but are not limited to:
- Multi-core performance
- Reliability of large systems
- Impact of technology on architecture
- Power-efficient architectures and techniques
- High-availability architectures
- High-performance I/O systems
- Embedded and reconfigurable architectures
- Interconnect and network interface architectures
- Network processor architectures
- Innovative hardware/software trade-offs
- Impact of compilers and OS on architecture
- Performance evaluation and modeling of real machines
A new two-part submission process is being used. Authors
must submit an abstract by Friday, April 6, 2007. They must submit
the full version of the paper by Monday, April 9, 2007. No
extensions will be granted. The full version should be a PDF file
that does not exceed 20 pages according to the instructions on
http://sc07.supercomputing.org. Papers that exceed the length
limit or that cannot be viewed using Adobe Acrobat Reader (version
3.0 or higher) may not be reviewed. Submissions for the Gordon
Bell Prize will be handled the same way. Please indicate if the
paper is a student paper for best student paper nominations.
Papers will be evaluated based on their novelty, fundamental
insights, and potential for long-term contribution. New-idea papers
are encouraged.
The submission site is http://www.sc-submissions.org/.
Submission issues for papers should be directed to
papers@xxxxxxxxxxxxxxxxxxxxxxxx
Workshop, tutorial, panel session and other submissions are also
solicited. See http://sc07.supercomputing.org.
Important dates:
- Abstracts due: April 6, 2007, 11pm EST
- Papers due: April 9, 2007, 11pm EST
- Workshop, panel, and tutorial proposals due: April 9, 2007, 11pm EST
- Notification of acceptance: July 2, 2007
Papers Committee Co-Chairs:
Ricky Kendall, Oak Ridge National Lab
Josep Torrellas, University of Illinois
Area Chairs:
Applications: Omar Ghattas, University of Texas
Architecture: John Carter, University of Utah
Grids: Marty Humphrey, University of Virginia
Anne Trefethen, Oxford University
Networks: Craig Stunkel, IBM
Performance: Adolfy Hoisie, Los Alamos National Lab
System Software: Keshav Pingali, University of Texas
Program Committee:
APPLICATIONS:
Srinivas Aluru, Iowa State University
George Biros, University of Pennsylvania
Christian Bischof, University of Aachen
Rupak Biswas, NASA Ames
Brett Bode, DOE Ames Laboratory
Nikos Chrisochoides, College of William and Mary
Charbel Farhat, Stanford University
Stephen Jardin, Princeton Plasma Physics Lab
Kwan-Liu Ma, University of California Davis
Esmond Ng, Lawrence Berkeley National Lab
Michael Norman, University of California San Diego
David O'Hallaron, Carnegie Mellon University
Padma Raghavan, The Pennsylvania State University
Ulrich Ruede, University of Erlangen-Nuremberg
P. (Saday) Sadayappan, The Ohio State University
Gerhard Wellein, Regionales RechenZentrum Erlangen
Theresa Windus, Iowa State University
ARCHITECTURE:
Dennis Abts, Cray
Doug Burger, University of Texas
Derek Chiou, University of Texas
Mark Heinrich, University of Central Florida
Jose Martinez, Cornell University
Viktor Prasanna, University of Southern California
Alex Ramirez, Universitat Politècnica de Catalunya
Ashley Saulsbury, Sun Microsystems
Xiaowei Shen, IBM
Yan Solihin, North Carolina State University
Lixin Zhang, IBM
GRIDS:
David Abramson, Monash University
Henrique Andrade, IBM
Henri Bal, Vrije Universiteit
Sujoy Basu, HP Labs
Franck Cappello, Inria
Ann Chervenak, USC Information Sciences Institute
Silvia Figueira, Santa Clara University
Wolfgang Gentzsch, D-Grid Initiative
Andrew Grimshaw, University of Virginia
Keith Jackson, Lawrence Berkeley National Lab
Dan Katz, Louisiana State University
Satoshi Matsuoka, Tokyo Institute of Technology
Philip Papadopoulos, San Diego Supercomputer Center
Manish Parashar, Rutgers University
Beth Plale, Indiana University
Rich Wolski, Univ. of California Santa Barbara
NETWORKS:
Alan Benner, IBM
Darius Buntinas, Argonne National Lab
Mitch Gusat, IBM
Rami Melhem, University of Pittsburgh
Jarek Nieplocha, Pacific Northwest National Lab
Vivek Pai, Princeton University
Scott Pakin, Los Alamos National Lab
Dhabaleswar Panda, The Ohio State University
Fabrizio Petrini, Pacific Northwest National Lab
Steven Scott, Cray
Keith Underwood, Sandia National Laboratories
Pete Wyckoff, OSC
Dongyan Xu, Purdue University
PERFORMANCE:
Bronis de Supinski, Lawrence Livermore National Lab
Vladimir Getov, University of Westminster
Lizy John, University of Texas
Karen Karavanic, Portland State University
Darren Kerbyson, Los Alamos National Lab
Barton Miller, University of Wisconsin
Bernd Mohr, Forschungszentrum Juelich
Leonid Oliker, Lawrence Berkeley National Lab
Allan Snavely, San Diego Supercomputer Center
Xian-He Sun, Illinois Institute of Technology
Jeffrey Vetter, Oak Ridge National Lab
Patrick Worley, Oak Ridge National Lab
SYSTEM SOFTWARE:
Greg Bronevetsky, Lawrence Livermore National Lab
Calin Cascaval, IBM
Rudolf Eigenmann, Purdue University
Guang Gao, University of Delaware
Mary Hall, USC Information Sciences Institute
Tony Hey, Microsoft
Laxmikant Kale, University of Illinois
Hironori Kasahara, Waseda University
Ken Kennedy, Rice University
Wei Li, Intel
Calvin Lin, University of Texas
Frank Mueller, North Carolina State University
David Padua, University of Illinois
Ram Rajamony, IBM
Lawrence Rauchwerger, Texas A&M University
Robert Wisniewski. IBM
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* WIOSCA 2007 Call for Papers: Workshop on the Interaction between Operating Systems
and Computer Architecture
~ Call for Papers ~
Workshop on the Interaction between
Operating Systems and Computer Architecture
( WIOSCA 2007)
http://www.ideal.ece.ufl.edu/wiosca
Held in Conjunction with the
34th Annual International Symposium on Computer Architecture
Part of the 2007 Federated Computer Research Conference
( ISCA - 34 )
Workshop Overview and Topics
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Operating systems (OS) constitute a major software component
and are essential to any computing system. Commercial and
server workloads such as online transaction processing,
database, file/e-mail servers involve significant OS-level
activity. The interactions between OS and emerging
architectures (e.g. homogeneous and heterogeneous chip
multiprocessors, simultaneous multithreading systems) /
technology (e.g. hardware-assisted virtualization) are
projected to continuously increase. To optimize system
performance/power/reliability/security, it is important to
facilitate efficient interaction and cooperation between the
two constantly evolving components - computer architecture and
OS.
This workshop focuses on characterizing, modeling, and
optimizing the interaction between OS and hardware in the
light of emerging architecture paradigms, workloads, and
computing technology. Topics of particular interest include,
but are not limited to:
* Architectural support for OS functionality and services
* OS support for emerging computer architectures
* Architectural support for virtual machines and hypervisors
* Implications of hardware virtualization on OS design
* Frameworks and tools for full-system simulation
* Techniques for mitigating the bottlenecks of OS execution
* OS-aware microarchitecture design
* Performance, power, dependability, and security in OS
* Evaluation of the interaction/interference between OS/user
* Workload variability issues full-system evaluation
* Effect of OS mechanisms on emerging architectures
* Characterization of OS activity in emerging workloads
* Leveraging OS to optimize reliability/thermal/power
Furthermore, the workshop aims at providing a forum for
researchers, engineers, and students from academia and
industry to discuss their latest research in computer
architecture and OS, to bring their ideas and research
problems to the attention of others, and to obtain valuable
and instant feedback from fellow researchers.
Workshop Co-Organizers
~~~~~~~~~~~~~~~~~~~~~~
Tao Li, University of Florida (taoli@xxxxxxxxxxx)
Sangyeun Cho, University of Pittsburgh (cho@xxxxxxxxxxx)
Onur Mutlu, Microsoft Research (onur@xxxxxxxxxxxxx)
Publicity/Publication Chair
~~~~~~~~~~~~~~~~~~~~~~~~~~~
James Poe, University of Florida (jpoe@xxxxxxx)
Program Committee
~~~~~~~~~~~~~~~~~
Richard Draves, Microsoft Research
Alexandra Fedorova, Simon Fraser University
Renato Figueiredo, University of Florida
Christos Kozyrakis, Stanford University
Hsien-Hsin S. Lee, Georgia Institute of Technology
Grigorios Magklis, Intel Barcelona
Chuck Moore, AMD
Feng Qin, Ohio State University
Steve Reinhardt, Reservoir Labs / University of Michigan
Yan Solihin, North Carolina State University
Brad Waters, Microsoft
Emmett Witchel, University of Texas at Austin
Min Xu, VMware
Jun Yang, University of Pittsburgh
Lixin Zhang, IBM
Submission Guidelines
~~~~~~~~~~~~~~~~~~~~~
1. Submit an abstract under 200 words by March 29, 2007.
2. Submit the full paper under 5,000 words by April 5, 2007.
The submission website will be linked from our website in
early March
Important Dates
~~~~~~~~~~~~~~~
* Abstract Submission: March 29, 2007
* Paper Submission: April 5, 2007.
* Author Notification: May 8, 2007.
* Camera-ready Version: May 15, 2007.
* Workshop will be held in San Diego, California on June 10.
Please feel free to visit our website for more information
as well as links to previous WIOSCA workshops:
http://www.ideal.ece.ufl.edu/wiosca
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* COOL Chips X Call for Posters: IEEE Symposium on Low-Power and High-Speed Chips
Call For Posters
IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips X
April 18-20, 2007
Yokohama, Japan
IMPORTANT DEADLINES:
-Posters:
Abstract Submission: March 12, 2007
Poster Acceptance Notified: March 19, 2007
-------------------------------------------------------------------------
COOL Chips is an International Symposium initiated in 1998 to present
advancement of low-power and high-speed chips. The symposium covers
leading-edge technologies in all areas of microprocessors and their
applications.
COOL Chips X is to be held in Yokohama on April 18-20, 2007, and is
targeted at the architecture, design and implementation of chips with
special emphasis on the areas listed below. The COOL Chips Organizing
Committee will ask the MICRO to publish selected papers in a special
issue on COOL Chips X.
Contributions are solicited in the following areas:
- Low Power-High Performance Processors for
Multimedia, Digital Consumer Electronics, Mobile, Graphics,
Encryption, Robotics, Networking and Biometrics.
- Novel Architectures and Schemes for
Single Core, Multi-Core, Embedded System, Reconfigurable Computing,
Grid, Ubiquitous, Dependable Computing and Wireless.
- Cool Software including
Binary Translations, Compiler Issues and Low Power Techniques.
- 10th Anniversary Special Topics:
Low Power, High Performance and High Efficiency Supercomputing.
Posters:
Submission should be made by e-mail to: Toshinori Sato, Poster Chair
poster_X@xxxxxxxxxxxxx
Extended abstract submissions should be ONE page, formatted using
standard two-column IEEE format. They are refereed primarily based on
their relevance to the conference. Accepted abstracts will be published
in the Proceedings of the COOL Chips X. All participants in this track
will have an opportunity to present a poster and a short talk.
Submission of a paper to the track signifies an agreement to have one
author present the work at the conference.
-------------------------------------------------------------------------
IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips X
Yokohama Joho Bunka Center, Yokohama, Japan
(Yokohama Media & Communications Center, Yokohama, Japan)
April 18 - 20, 2007
http://www.coolchips.org/
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Keynote Presentations:
- Introduction of the Japanese Supercomputer Project and its Technical
Challenges, Tadashi Watanabe (RIKEN)
- Toshiba's Strategy in Semiconductor Business and NAND Flash Memory,
Shozo Saito (Toshiba Corp.)
Invited Presentations:
- A 65nm SPE for a 1 Petaflop Super Computer, Brian Flachs (IBM)
- EXREAL Platform : SOC Design Challenges for Embedded Systems,
Toshihiro Hattori (Renesas Technology Corp.)
Panel Discussion: 10th Anniversary Special Topics
- Microprocessor for 10-PetaFLOPS supercomputer, organizer & moderator:
Ryutaro Himeno (RIKEN)
Special Sessions:
- Novel Architectural Techniques to Mitigate Processor Errors due to
Design Defects and Parameter Variation, Josep Torrellas (University of
Illinois)
- Architectural Integration of Software Protection, Gyungho Lee
(University of Illinois)
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* ACACES 2007 Call for Participation: Third International Summer School on Advanced
Computer Architecture and Compilation for Embedded Systems
ACACES 2007 Call for participation
Third International Summer School on
Advanced Computer Architecture and Compilation
for Embedded Systems
L'Aquila, Italy
Sunday July 15 - Saturday July 21, 2007
Organized by the HiPEAC Network of Excellence
sponsored by the 6th European framework programme
http://www.hipeac.net/summerschool
The ACACES Summer School is a one week summer school for computer architects
and compiler builders working in the field of high performance computer
architecture and compilation for embedded systems. The school aims at the
dissemination of advanced scientific knowledge and the promotion of
international contacts among scientists from academia and industry.
A distinguishing feature of this Summer School is its broad scope ranging
from low level technological issues to advanced compilation techniques. In
the design of modern computer systems one has to be knowledgeable about
architecture as well as about the quality of the code, and how to improve
it. This summer school offers the ideal mix of the two worlds, both at
the entry level and at the most advanced level.
The ACACES Summer School is organized by the HiPEAC Network of Excellence
(http://www.HiPEAC.net), but it is open to everybody. However, previous
training and/or experience in computer science as well as a background in
computer architecture or compilation is indispensable.
The Summer School will take place in L'Aquila, a small town about 100 km
northeast of Rome, the capital town of Abruzzi and of the Province of
L'Aquila. It will be held at the excellent facilities of the Telecom Italia
Learning Services Campus, located on a small hill a few kilometers away from
the center of L'Aquila.
Students and lecturers will be accommodated in private rooms with standard
hotel accommodation on campus, and they will stay on campus for one week.
Hence, there will be lots of opportunities for interaction among the
participants, both in and out the classrooms, during the meals, at the bar
or at the pool table. Long after-the-lecture discussions are one of the
major assets of this summer school. You will remember this summer school
for a long time.
Scientific program
------------------
Sunday July 15: Opening ceremony with a keynote talk
Starting on Monday 16, 2007:
12 courses spread over two morning slots and two afternoon slots. Per slot
there are three parallel courses of which one can be taken. The topics
of this year's Summer School will be presented by the following world-class
experts in their domain.
- Pradip Bose, IBM, USA
Power-efficient, reliable micro-architectures
- Jack Davidson, University of Virginia, USA
Compilation Techniques for Embedded Systems
- Michel Dubois, University of Southern California, USA
Coherence, Store Atomicity and Memory Consistency Models
- Paolo Faraboschi, Hewlett Packard Laboratories, Spain
Embedded VLIW Architectures and Compilers
- Manolis Katevenis, FORTH and Univ. of Crete, Greece
Queueing and Flow Control in Interconnection Switches
- Peter Marwedel, University of Dortmund, Germany
Memory architecture aware compilation
- Kathryn McKinley, University of Texas at Austin, USA
Optimizing and Measuring Managed Languages
- Kunle Olukotun, Stanford University, USA
Chip Multiprocessor (CMP) Architectures
- Lawrence Rauchwerger, Texas A&M University, USA
Parallel Programming Models
- Barbara Ryder, Rutgers University, USA
Advanced Program Analyses for Object-oriented Systems
- Guri Sohi, University of Wisconsin-Madison, USA
Memory Dependence Prediction and its Applications
- Hans van Someren, ACE Associated Compiler Experts, The Netherlands
Constructing Compiler Components for Reusability
Sunday evening keynote: Hugo De Man, IMEC.
Wednesday afternoon: Poster session
Friday evening: Farewell dinner and party
Certificate
-----------
All participants will receive a certificate of attendance with a
description of the courses followed. Some universities will accept
this certificate in their PhD program.
Poster Session
--------------
The poster session on Wednesday afternoon will provide an ideal
opportunity for students to present their own work in progress
and get feedback from senior researchers and fellow-students,
and can be the beginning of future collaboration. A booklet with
a 1 to 4 page abstract per poster will be distributed to all
summer school participants.
Admission
---------
To stimulate maximum interaction between lecturers and
participants, the steering committee of the Summer School will
admit a limited number of participants. The application
form is on the website, and the deadline for application is
April 1, 2007.
Important dates
---------------
April 1, 2007: deadline for admission application
May 1, 2007: notification of admission
June 1, 2007: deadline for registration
June 1, 2007: deadline for poster abstract
Registration
------------
990 euro, all inclusive:
- Transfer from Rome to L'Aquila by bus on Sunday July 15, 2007.
- 6 nights in an on campus private air-conditioned room with bathroom.
- 6 breakfasts (choice between continental and American-style breakfast)
- 5 hot lunches consisting of 2 courses, a dessert, and wine/water
- 5 dinners consisting of 2 courses, a dessert, and wine/water
- Farewell dinner on Friday evening
- 2 half-hour coffee breaks per day
- Registration for 4 top-quality courses + printed handouts
- Student kit
- Access to the poster session + book of abstracts
- Free Internet during the duration of the summer school
- Free access to the sports facilities of the campus
- Free transfer from L'Aquila to Fiumicino airport or to downtown Rome on
Saturday July 21, 2007.
Steering Committee
------------------
- Koen De Bosschere, Ghent University, Belgium, Chair
- Josep Llosa, UPC, Barcelona, Spain
- Mike O'Boyle, University of Edinburgh, UK
- Antonio Prete, University of Pisa, Italy
- Olivier Temam, INRIA Futurs, Orsay, France
- Theo Ungerer, University of Augsburg, Germany
- Mateo Valero, UPC, Barcelona, Spain
Contact information
-------------------
Koen De Bosschere
acaces@xxxxxxxxxx
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----------------------------------------------------------------------
* WCAE 2007 Call for Papers: Workshop on Computer Architecture Education
Workshop on Computer Architecture Education
Held in conjunction with the
34th International Symposium on Computer Architecture
San Diego, CA
Saturday, June 9, 2007
http://www4.ncsu.edu/~efg/wcae2007.html
Theme
WCAE provides the premier forum for educators in computer architecture
to discuss and share their experiences and teaching philosophy. Over
190 papers on computer architecture education have been presented at
the workshop since its inception in 1995. The goal is for participants
to come away from the workshop with new ideas on delivering courses in
computer architecture. Topics of interest include, but are not limited
to, the following.
Topics of interest
New approaches to introductory courses
Advanced courses
Development of materials for active learning
Laboratory support for distance education
Textbook development
Textbook selection
Critical evaluation of textbook approaches
Integration of research into teaching
Industrial support for teaching
Interdepartmental issues (CS/ECE)
National differences in curricula
Hardware tools
Simulators and other software tools
Prototyping
Visualization aids
VLSI design packages
Architectural issues specific to embedded systems
Software issues specific to embedded systems
Industrial needs regarding embedded systems education
Encouraging students to do research
Encouraging students to pursue the Ph.D.
For an idea of what we have published in the past, see the WCAE
archive, http://www.ncsu.edu/wcae/, made possible with funding from
the SIGCSE Special Projects fund.
Submission of contributions
Interested authors should submit a full paper (not to exceed 8 pages),
following the formatting instructions given in the files in
ftp://pubftp.computer.org/Press/Outgoing/proceedings/8.5x11%20-%20Formatting%20\
files/
Organizer
Edward F. Gehringer
e-mail: efg@xxxxxxxx
Center for Efficient, Secure and Reliable Computing
Dept. of Electrical and Computer Engineering
Department of Computer Science
North Carolina State University
Box 7256
Raleigh, NC 27695-7256
+1 919 515-2066
Important Dates
Submission Due Date: Monday, April 30, 2007
Author Notification: Friday, May 11, 2007
Final Paper Due Date: Friday, May 18, 2007
Copies of papers presented at the workshop will be made available at the worksh\
op, and in archival form on the Web.
Program Committee
Aleksandr Milenkovic, University of Alabama at Huntsville
Anujan Varma, University of California at Santa Cruz
Chris Vickery, City University of New York
Craig Zilles, University of Illinois
Dan Connors, University of Colorado
David Kaeli, Northeastern University
Diana Franklin, Cal Poly-San Luis Obispo
Eduardo Sanchez, Ecole Polytechnique Federale, Lausanne
James Conrad, University of North Carolina at Charlotte
Joerg Keller, Fernuniversitaet Hagen
Joao Cardoso, INESC-ID, Lisbon
Manish Vachhajarani, University of Colorado
Mark Fienup, University of Northern Iowa
Mats Brorsson, KTH Royal Institute of Technology, Stockholm
Michael Manzke, Trinity College, Dublin
Antonio Prete, Università di Pisa
Mitch Thornton, Southern Methodist University
Richard Enbody, Michigan State University
Subramanian Ganesan, Oakland University
Tim Stanley, Brigham Young University-Hawaii
Wayne Wolf, Princeton University
Yale Patt, University of Texas at Austin
----------------------------------------------------------------------
----------------------------------------------------------------------
* TRANSACT '07 Call for Papers: The Second ACM SIGPLAN Workshop on Transactional Computing
| CALL FOR PAPERS |
| |
| TRANSACT '07 |
| The Second ACM SIGPLAN Workshop on Transactional Computing |
| |
| To be held in conjunction with PODC 2007 |
| Portland, Oregon, August 16, 2007 |
WORKSHOP WEBSITE: www.cs.rochester.edu/meetings/TRANSACT07/
The past few years have seen an explosion of interest in programming
languages, systems, and hardware to support transactions, speculation,
and related alternatives to classical lock-based concurrency. This
workshop, the second in its series, will provide a forum for the
presentation of research on all aspects of transactional computing.
The scope of the workshop is intentionally broad, with the goal of
encouraging interaction across the languages, architecture, systems,
database, and theory communities. Papers may address implementation
techniques, foundational results, applications and workloads, or
experience with working systems. Environments of interest include the
full range from multithreaded or multicore processors to high-end
parallel computing.
Specific topics of interest include (but are not limited to):
* Runtime systems * Language mechanisms and semantics
* Hardware support * Static analysis and compiler optimizations
* Memory models * Conflict detection and contention management
* Persistence and I/O * Long-running or distributed transactions
* Nesting and exceptions * Communication among transactions
* Speculative concurrency * Checkpointing and failure atomicity
* Formal verification * Applications, workloads, and test suites
* Debugging and tools * Interaction w/ lock-based or nonblocking code
* Migration from legacy systems
Papers should present original research and should provide sufficient
background material to make them accessible to the broader community.
Papers focused on foundations should indicate how the work can be used
to advance practice; papers on experiences and applications should
indicate how the experiments reinforce principles.
PAPER SUBMISSION:
Papers must be submitted in Postscript or PDF format, and must be no
more than 8 pages in length in standard two-column SIGPLAN conference
format. Shorter submissions are also welcome.
On-line submission via the workshop website will be available no later
than 15 March.
Hard copies of final papers (up to 10 pages in length) will be
distributed at the meeting, but to facilitate re-submission to more
formal venues, no archival proceedings will be published. Authors will
have the option of having electronic copy of their final paper
accessible from the workshop website or other on-line repository. At
the discretion of the program committee (and with the consent of the
authors), particularly worthy papers may be recommended for a special
journal issue.
IMPORTANT DATES:
Submissions due: April 15, 2007
Notification: June 1, 2007
Final copy due: July 1, 2007
Workshop: August 16, 2007
Program Chair: Michael L. Scott, University of Rochester
General Chair: Raschid Guerraoui, Ecole Polytechnique Federale de Lausanne
PROGRAM COMMITTEE:
Ali-Reza Adl-Tabatabai, Intel Corporation
Anastassia Ailamaki, Carnegie Mellon University
Hagit Attiya, Technion
Goetz Graefe, HP Labs
Mark Hill, University of Wisconsin - Madison
Suresh Jagannathan, Purdue University
Christos Kozyrakis, Stanford University
Bradley C. Kuszmaul, MIT
Victor Luchangco, Sun Labs
Jan-Willem Maessen, Sun Labs
Martin Odersky, Ecole Polytechnique Federale de Lausanne
Simon Peyton-Jones, Microsoft Research
Ravi Rajwar, Intel Corporation
William N. Scherer III, Rice University
STEERING COMMITTEE:
Tim Harris, Microsoft Doug Lea, SUNY Oswego
Maurice Herlihy, Brown Eliot Moss, UMass
Tony Hosking, Purdue Jan Vitek, Purdue
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* IISWC 2007 Call for Benchmarks: The Annual 2007 IEEE International Symposium on Workload
Characterization (IISWC)
The Annual 2007 IEEE International Symposium on Workload Characterization (IISWC)
http://www.iiswc.org/
Sept 27-29, 2007 - Boston, MA
*** CALL FOR BENCHMARKS ***
IISWC is building a set of benchmarks to distribute to researchers. You are invited to
participate in the creation of this benchmark set. In addition to the normal paper
submissions, IISWC will accept "benchmark submissions". These comprise C, C++, C# or Java
code, inputs to the code, and an associated six-page paper. The goal of the paper should be
to explain the benchmark, what it does, and why it is relevant to a particular user
community. Benchmark authors should be willing to allow distribution of source code and
input sets. Code must be open source consistent with the GNU general public license,
see http://www.gnu.org/licenses.
We encourage software developers to submit benchmarks from any application domain,
especially from under-represented and emerging domains. Example workload areas of interest
are, but not limited to, data mining, bioinformatics, virtualization, gaming, 3D, graphics,
biometrics, security, embedded, mobile, multimedia, etc. We especially encourage
multithreaded and transactional memory benchmark submissions. Also, benchmarks written in
emerging programming languages are of great interest.
The criteria that will be used to judge benchmark submissions include:
* significance of the benchmark to a user community,
* ease of use,
* quality of the benchmark write-up, and
* portability of the submitted code.
Successful submissions will be included in the IISWC benchmark set and their associated
descriptive short six-page papers will be published in the IISWC proceedings.
Important Dates: Paper and Benchmark Submission: April 15, 2007
Notification: May 28, 2007
Submissions will be in the form of a webpage that will include documentation on the
benchmark, source code and benchmark inputs. Send all submissions to Lieven Eeckhout at
leeckhou@xxxxxxxxxxxxxx
Committee : Lieven Eeckhout (chair), Ghent University
Kevin Lepak, AMD
Alex Ramirez, Barcelona Supercomputing Center & UPC
Sami Yehia, ARM
Tim Sherwood, University of California, Santa Barbara
Yan Solihin, North Carolina State University
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* PACT '07: 16th International Conference on Parallel Architectures
and Compilation Techniques
16th International Conference on Parallel Architectures and Compilation Techniques
(PACT '07)
http://pactconf.org
Brasov, Romania
September 15-19, 2007
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* Call for Papers Special Issue: Circuits and Systems for Real-Time Security and
Copyright Protection of Multimedia
Call for Papers Special Issue: Circuits and Systems for Real-Time Security and Copyright Protection of Multimedia
International Journal of Computers and Electrical Engineering (Elsevier Ltd.)
(http://www.elsevier.com/wps/find/journaldescription.cws_home/367/description)
Guest Editor(s):
-- Saraju P. Mohanty, University of North Texas, email: smohanty@xxxxxxxxxxxx
-- Nasir Memon, Polytechnic University, email: memon@xxxxxxxxx
-- Karam S. Chatha, Arizona State University, email: kchatha@xxxxxxxx
Following the explosive growth of the Internet, concerns about protection and enforcement of IP rights of digital content involved in transactions have been mounting. Easy unauthorized replication and manipulation with inexpensive tools has worsened the scenario. Due to this, the movie/audio industry loses several billions of dollars every year. Hence, DRM (Digital Rights Management) systems are necessary for establishing ownership rights, tracking usage, ensuring authorized access, preventing illegal replication, and facilitating content authentication. Such DRM systems may need various techniques including, encryption, watermarking, steganography, scrambling, digital certificates, secure communications protocols, etc. In the last decade, significant research progress has been made to develop these techniques which primarily work offline. However, in case of emerging applications, such as, digital television broadcasting, internet protocol television (IP-TV), video on deman!
d, pay-TV, electronic passport (e-passport), credit cards, driving licenses, etc. security and copyright protection mechanisms have to work in real-time. Consequently, appliances, like digital cameras, network processors, mobile/video phones, graphics processing units, DVD player, etc. need to be equipped with such mechanisms. In these situations, software only solutions may not be adequate to provide real-time performance, rather hardware assisted solutions is needed for easy integration with multimedia hardware, low-power consumption, higher reliability/availability, and low-cost compared.
The guest editors invite original manuscripts addressing the above challenges. The topics of research interest include, but not limited to:
-- Real-time performance integrated circuits for DRM techniques.
-- Operating-system and (micro) architecture-level support for security and copyright protection.
-- Methods to integrate security and copyright protection mechanism in embedded architectures.
-- Building SoCs such as camera, mobile phones, network processors with DRM technology.
-- Building media processors, graphics processing units with DRM technology.
-- Techniques for secure multimedia broadcasting in wireless systems.
-- Security and copyright techniques for home entertainment, such as IP-TV and digital TV, etc.
-- Techniques for real-time multimedia processing in encryption and/or watermarking domain.
-- Design of side-channel-resistant embedded systems to enable attack-proof DRM development.
-- Low-power DRM technology for portable appliances.
Submission Information: Manuscripts should be emailed to the guest editors (smohanty@xxxxxxxxxxx and memon@xxxxxxxx and kchatha@xxxxxxx) as pdf files. The maximum page limit for a manuscript is 25 pages. The pdf file should be named using last name of the first author followed by a keyword from the paper title. For example, the filename for authors S. Mohanty and N. Memon submitting the paper titled: "On Watermarking Techniques Developments" would be Mohanty-Watermarking. Guidelines for manuscript preparation can be found at:
http://www.elsevier.com/wps/find/journaldescription.cws_home/367/authorinstructions.
Schedule:
-- Paper Submission Deadline: 15th June 2007
-- Notification of Acceptance or Request for Revision (if any): 15th August 2007
-- Notification of Revised Papers Acceptance: 31st August 2007
-- Camera Ready Final Version Due: 30th September 2007
-- Appearance of Special Issue: December 2007 / Early 2008
Questions and More Information: Please feel free to contact the guest editors.
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