This is the 1st August 2007 Digest of SIGARCH Messages (sigarch-aug07a):
* HPCA-08 Call for Papers: 14th International Symposium on High-Performance Computer Architecture
http://www.cs.utah.edu/hpca08/
Submitted by Liqun Cheng <legion@xxxxxxxxxxx>
* Hot Chips 2007 Call for Participation: Hot Chips 2007, August 19-21, 2007, Stanford University; Palo Alto, California
http://www.hotchips.org
Submitted by Don Draper <ddraper@xxxxxxxxxx>
* IISWC 2007 Final Program: IEEE Intl Symposium on Workload Characterization
http://www.iiswc.org
Submitted by Bhuvan Urgaonkar <bhuvan@xxxxxxxxxxx>
--Doug Burger
SIGARCH Chair
infodir_SIGARCH@xxxxxxx
* Archive: http://lists.cs.wisc.edu/archive/sigarch-members/
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Doug Burger Office: 3.432 ACES
Associate Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
The University of Texas at Austin Fax: 512-232-1413
1 University Station, #C0500 E-mail: dburger@xxxxxxxxxxxxx
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* HPCA-08 Call for Papers: 14th International Symposium on High-Performance Computer Architecture
HPCA-08 Call for Papers
14th International Symposium on High-Performance Computer Architecture
Salt Lake City, Feb. 16-20, 2008, (collocated with PPoPP?08)
http://www.cs.utah.edu/hpca08/
Submissions of Abstracts: Aug. 7th, 2007 at 1PM EST
Submissions of Full Papers: Aug. 14th, 2007 at 1PM EST
Notifications for Technical Paper: October 27, 2007
The International Symposium on High-Performance Computer Architecture is a
premier forum for scientists and engineers to present their latest
research findings in this rapidly-changing field. Authors are invited to
submit papers on all aspects of high-performance computer architecture.
Topics of interest include, but are not limited to:
* Processor architectures
* Cache and memory systems
* Parallel computer architectures
* Impact of technology on architecture
* Power-efficient architectures and techniques
* Dependable architectures
* High-performance I/O systems
* Embedded and reconfigurable architectures
* Special purpose processors and accelerators
* Interconnect and network interface architectures
* Network processor architectures
* Innovative hardware/software trade-offs
* Impact of compilers and operating systems on architecture
* Performance modeling and evaluation
Authors should submit an abstract before Tuesday, August 7, 2007, 1pm EST.
They should submit the full version of the paper before Tuesday, August
14, 2007, 1pm EST. No extensions will be granted. The full version should
be a PDF file that does not exceed 6,000 words according to the
instructions in http://www.cs.utah.edu/hpca08/. Papers that exceed the
length limit or that cannot be viewed using Adobe Acrobat Reader (version
3.0 or higher) may not be reviewed. Papers should be submitted for blind
review. Please contact one of the program co-chairs for any submission
issues.
HPCA will host an Industrial Paper Session presenting novel insights from
industry. Its separate Call for Papers can be found at
http://www.cs.utah.edu/hpca08/. Papers will be evaluated based on their
novelty, fundamental insights, and potential for long-term contribution.
New-idea papers are encouraged.
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* Hot Chips 2007 Call for Participation: Hot Chips 2007, August 19-21, 2007
Stanford University; Palo Alto, California
HOT Chips 19 ADVANCE PROGRAM
A Symposium on High-Performance Chips
August 19-21, 2006, Memorial Auditorium,
Stanford University, Palo Alto, California
HOT Chips brings together designers and architects of high-performance
chips, software, and systems. Presentations focus on up-to-the-minute
real developments. This symposium is the primary forum for engineers and
researchers to highlight their leading-edge designs. Three full days of
tutorials and technical sessions will keep you on top of the industry.
See http://www.hotchips.org for registration information, local
arrangements, location, etc.
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Sunday, August 19, 2007
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Morning Tutorial:
Approaches to System Design for the Working Engineer
Part 1 ASICs and ASSPs - David Witt (Texas Instruments)
Part 2 FPGAs, from Glue Logic to Systems Components: Twenty Years of FPGA Evolution
- Peter Alfke (Xilinx)
Part 3 Exploiting Chip-Level Processor Heterogeneity through Fine-Grained Reconfigurable
Interactions
- Shephard Siegel (Mercury Computer Systems)
Lunch
Afternoon Tutorial
Enterprise Power and Cooling: A Chip-to-Data Center Perspective
Chandrakant Patel (HP Labs)
Parthasarathy Ranganathan (HP Labs)
Part I: Background
Part II: Cooling: A Chip-core to Cooling-Tower Perspective
Part III: Power: From Chips to Data Centers
Part IV: Case Study and Future Directions
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Monday, August 20, 2007
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Opening Remarks
IBM Power6
* Fault-Tolerant Design of the IBM POWER6 Microprocessor (IBM)
* System Performance Scaling of IBM POWER6 Based Servers (IBM)
* The Third Generation of IBM's Elastic Interface (EI-3) Implementation on
POWER6(TM) (IBM)
Keynote 1: Vernor Vinge, computer scientist and science fiction writer who has novelized
potential interactions between machines and humans, author of True Names and
Rainbows End.
Lunch
Multi-core & Parallelism A
* NVIDIA GeForce 8800 GPU (NVIDIA)
* The NVIDIA GPU Parallel Computing Architecture (NVIDIA)
* Performance Insights of Executing Non-Graphics Applications on the NVIDIA
GeForce 8800(TM) and the CUDA(TM) Parallel Programming Environment (UIUC)
Multi-core & Parallelism B
* Radeon R600 Technology, a 2nd Generation Unified Shader Architecture (AMD)
* Teraflop Prototype Processor with 80 Cores (Intel)
* Design and Implementation of the TRIPS Prototype Chip (UT Austin)
* The Tile Processor: Embedded Multicore for Networking and Digital Multimedia
(Tilera Corporation)
Embedded and Video
* SH-X3: Flexible SuperH Multi-Core for High-Performance and Low-Power Embedded
Systems (Renesas)
* An Innovative HD Video and Digital Image Processor for Low-Cost Digital
Entertainment Products (Texas Instruments)
* Professional H.264/AVC CODEC Chip-Set for High-Quality HDTV Broadcast
Infrastructure and High-End Flexible CODEC Systems (NTT)
Dinner
Panel: What's next beyond CMOS?
Chair: Norm Jouppi (Hewlett Packard)
Panelists:
Mark Horowitz (Stanford University)
John Kubiatowicz (UC Berkeley)
Mike Mayberry (Intel)
Ghavam Shahidi (IBM)
Stan Williams (Hewlett Packard)
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Tuesday, August 21, 2007
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Technology and Software Directions
* Multiterabit Switch Fabrics Enabled by Proximity Communication (Sun) Memory
Technology for Nano-Scale CMOS (T-RAM Semiconductor)
* Raksha: A Flexible Architecture for Software Security (Stanford)
Wireless
* A 4 Gbps Wireless Uncompressed 1080p-Capable HD A/V Transceiver using 60 GHz
(SiBeam)
* A 2x2 MIMO Baseband for High-Throughput Wireless Local-Area Networking (802.11n)
(Broadcom)
Keynote 2:
* Multicore and Beyond: Evolving the X86 Architecture
Phil Hester (CTO AMD)
Lunch
Networking
* A Packet Processing Chip Set (Cisco)
* Chesapeake: A 50Gbps Combined Network Processor and Traffic Manager
(Bay Microsystems)
* A System on a Chip with Integrated Accelerators (Intel)
* Focalpoint II, A Low-Latency, High Bandwidth Switch/Router Chip
(Fulcrum Microsystems)
Mobile PC Processors and Chipsets
* Advanced Power Management Features in Penryn - 45nm Next Generation Intel Core(TM)2
Duo Microarchitecture (Intel)
* Next Generation Mobile X86 Processor (AMD)
* nForce 680i and 680, NVIDIA's Next Generation Platform Processors
(NVIDIA)
Big Iron
* VictoriaFalls - Scaling Highly-Threaded Processor Cores (Sun)
* The Next-Generation Mainframe Microprocessor (IBM)
Special Presentation
* "Wireless Broadband and Entrepreneurship in America" Reed Hundt
(Frontline Wireless. Former chair FCC)
This is a preliminary program; changes may occur. For the most up-to-the-minute details
on presentations and schedules, and for registration information, please visit our web
site where you can also check out HOT Interconnects (another HOT Symposium being held
following HOT Chips):
Website: http://www.hotchips.org
Email: info2007@xxxxxxxxxxxx
Registration:
Early Registration: June 1, 2007 to July 31, 2007
Tutorials Only Conference Only Both
ACM/IEEE Members $100 $295 $395
Non-Members $125 $395 $520
Student Members $85 $85 $170
Student Non-Members $90 $110 $200
Late Registration: After July 31st, 2007
Tutorials Only Conference Only Both
ACM/IEEE Members $175 $475 $650
Non-Members $200 $575 $775
Student Members $95 $145 $240
Student Non-Members $100 $150 $250
Registration fees for Tutorials include a printed set of tutorial notes,
continental breakfast, lunch, coffee break, and invitation to the evening
Wine and Cheese Reception on Sunday, August 19, 2007.
Registration fees for the Conference include a flash drive containing a
set of the conference proceedings (printed sets are available for
purchase with advance registration), Monday night dinner, continental
breakfasts, lunches and coffee breaks during the two days
(August 20-21, 2007) of the conference. It also includes an invitation to
the evening Wine and Cheese Reception on Sunday, August 19, 2007.
Organizing Committee:
General Chair: John Sell Microsoft
Vice Chair: Don Draper Rambus
Finance: Lily Jow HP
Publicity: Kevin Krewell NVIDIA
Gail Sachs Telairity
Advertising: Don Draper Rambus
Sponsorship: Amr Zaky Broadcom
Publications: Gordon Garb Sun
Registration: Ravi Rajamani Oracle
Sujata Ramasubramanian Intel
Local Arrangements: Lance Hammond Apple
Webmaster: Alexis Cordova
Steering Committee:
Don Alpert Camelback Arch.
Allen Baum Intel
Pradeep Dubey Intel
Lily Jow HP
John Mashey Techviser
Howard Sachs Telairity
Alan Jay Smith UC Berkeley
Program Committee Co-Chairs:
Rajeevan Amirtharajah UC Davis
John Mashey Techviser
Program Committee:
Forrest Baskett NEA
Dileep Bhandarkar Microsoft
Doug Burger UT Austin
Christos Kozyrakis Stanford
Norm Jouppi HP Labs
John Montrym NVIDIA
Chuck Moore AMD
Mitsuo Saito Toshiba
Alan Jay Smith UC Berkeley
Marc Tremblay Sun Micro
Jan-Willem van de Waerdt NXP Semiconductors
Ralph Wittig Xilinx
Founder: Bob Stewart SRE
Hot Chips is A Symposium of the Technical Committee on Microprocessors
and Microcomputers of the IEEE Computer Society and the IEEE Solid
State Circuits Society
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* IISWC 2007 Final Program: IEEE Intl Symposium on Workload Characterization
The program for IEEE Intl Symposium on Workload Characterization (IISWC 2007)
is now finalized. The symposium features an exciting technical
conference comprising excellent papers from a diverse set of areas,
two keynote speeches by distinguished speakers, and two tutorials.
A summary of the program appears below and may also be found at:
available at: http://www.iiswc.org.
Please consider attending!
2007 IEEE International Symposium on Workload Characterization (IISWC 2007)
Where: Four Point Sheraton Logan Airport, Boston, MA, USA When: September 27-29 2007
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Program at a glance
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Thursday, September 27
8:00 a.m. - 8:30 a.m. Breakfast and Registration
8:30 a.m. - 8:45 a.m. Welcome Remarks
8:45 a.m. - 9:45 a.m. Keynote Speech I
10:15 a.m. - 12:15 p.m. Technical Session: Prediction
and Implications on Application Performance
1:30 p.m. - 3:00 p.m. Technical Session: Multi-core
3:30 p.m. - 4:30 p.m. Technical Session: Benchmark Studies
4:45 p.m. - 6:00 p.m. Panel Session
Friday, September 28
8:00 a.m. - 8:45 a.m. Breakfast
8:45 a.m. -9:45 a.m. Keynote Speech II
10:15 a.m. - 12:15 p.m. Technical Session: Benchmarks
1:30 p.m. - 3:00 p.m. Technical Session: Tracing and Online
Characterization
3:30 p.m. - 4:30 p.m. Technical Session: Data Center Applications
4:30 p.m. - 6:00 p.m. Technical Session: Compact Workload Creation
Saturday, September 29
Morning session Tutorial I
Afternoon session Tutorial II
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Detailed technical program
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Thursday, September 27
8:00 a.m. - 8:30 a.m. Breakfast and Registration
8:30 a.m. - 8:45 a.m. Welcome Remarks
8:45 a.m. - 9:45 a.m. Keynote Speech I
The SPEC Gorilla Turns One. So What?
John Henning, Sun Microsystems
SPEC CPU2006 is a 500 pound gorilla of benchmarking, with 1300 results published since its
release one year ago (24 August 2006), despite consuming vastly more time and computational
resources than its predecessor suites.
What have we learned about its workloads during its first year of life? Are there surprises
lurking in the code, workloads, or run rules that are difficult to simulate? What
characteristics of CPU2006 have proven successful? What does SPEC need to improve in
successor suites? Some proposed answers will be provided and time will be reserved for an
open microphone. The presenter will also be available during breaks to listen to feedback
about the suite.
A collection of eleven technical articles about SPEC CPU2006 will be given away; sit near
the front of the room to improve your chances of receiving a hard copy.
John L. Henning is a Performance Engineer at Sun Microsystems and is Secretary for the SPEC
CPU Subcommittee. He has contributed to performance analysis and improvement of software on
PDP-11, VAX, Alpha, and SPARC systems, including, in 1980, an implementation of a client/
server text processing workload based on observed user workloads. His first successful
performance project was shrinking a SORT process on an IBM 360/30 from 8 hours to 20 minutes.
This speedup was accomplished by improving the match between the user requirements, the
available computational resources, and the workload.
9:45 a.m. - 10:15 a.m. Break
10:15 a.m. - 12:15 p.m. Predicting and Implications on Application
Performance
Characterizing the Effect of Microarchitecture Design Parameters on Workload Dynamic Behavior
Chang-Burm Cho, Wangyuan Zhang, Tao Li, University of Florida
Implications of Conflict Rate Trends for Robust Software Transactional Memory
Craig Zilles, University of Illinois at Urbana-Champaign; Ravi Rajwar, Intel Corporation
Predicting Program Behavior Based On Objective Function Minimization
Ruhi Sarikaya, Alper Buyuktosunoglu, IBM Research
On the Effects of Memory Latency and Bandwidth on Supercomputer Application Performance
Richard C. Murphy, Sandia National Laboratories
12:15 p.m. - 1:30 p.m. Lunch
1:30 p.m. - 3:00 p.m. Multi-core
Evaluation of Server Consolidation Workloads for Multi-core Designs
Natalie Enright Jerger, Dana Vantrease, Mikko H. Lipasti, University of Wisconsin - Madison
Performance Studies of Commercial Workloads on a Multi-core System
Jessica H. Tseng, Hao Yu, Shailabh Nagar, Niteesh Dubey, Hubertus Franke, Pratap Pattnaik,
Hiroshi Inoue, Toshio Nakatani, IBM Research
Addressing Cache/Memory Overheads in Enterprise Java CMP Servers
Kumar Shiv, Mahesh Bhat, Mike Jones, Ramesh Illikal, Srihari Makineni, Don Newell,
Jason Domer, Ravi Iyer, Intel
3:00 p.m. - 3:30 p.m. Break
3:30 p.m. - 4:30 p.m. Benchmark Studies
Benchmarking BGP Routers
Qiang Wu, Yong Liao, Tilman Wolf, Lixin Gao, University of Massachusetts
Characterizing and Improving the Performance of Bioinformatics Workloads on the POWER5
Architecture
Vipin Sachdeva, Evan Speight, Mark W. Stephenson, IBM Research; Lei Chen, IBM Systems
and Technology Group
4:45 p.m. - 6:00 p.m. Panel Session
Benchmarking in the Web 2.0 Era
Moderator: Sudhanva Gurumurthi, University of Virginia
Friday, September 28
8:00 a.m. - 8:45 a.m. Breakfast
8:45 a.m. - 9:45 a.m.
Keynote Speech II
Taking Concurrency Seriously: the Multicore Challenge
Maurice Herlihy, Brown University
Computer architecture is undergoing, if not another revolution, then a vigorous shaking-up.
The major chip manufacturers have, for the time being, simply given up trying to make
processors run faster. Instead, they have recently started shipping "multicore''
architectures, in which multiple processors (cores) communicate directly through shared
hardware caches, providing increased concurrency instead of increased clock speed. As a
result, system designers and software engineers can no longer rely on increasing clock speed
to hide software bloat. Instead, they must somehow learn to make effective use of increasing
parallelism. This adaptation will not be easy. Conventional synchronization techniques based
on locks and conditions are unlikely to be effective in such a demanding environment.
Transactional memory is a computational model in which threads synchronize by transactions.
This synchronization model promises to alleviate many (perhaps not all) of the problems
associated with locking, and there is a growing community of researchers working on both
software and hardware support for this approach. This talk will survey the area, with a focus
on open research problems.
Maurice Herlihy has an A.B. in Mathematics from Harvard University and a Ph.D. in Computer
Science from MIT. He has been an Assistant Professor in the Computer Science Department at
Carnegie Mellon, a member of research staff at Digital Equipment Corporation's Cambridge (MA)
Research Lab, and a consultant for Sun Microsystems. He is now a Professor of Computer
Science at Brown University. His 1991 paper "Wait-Free Synchronization" won the 2003 Dijkstra
Prize in Distributed Computing, and he shared the 2004 Goedel Prize for his 1999 paper
"The Topological Structure of Asynchronous Computation." He is a Fellow of the ACM.
9:45 a.m. - 10:15 a.m. Break
10:15 a.m. - 11:45 a.m. Benchmarks
Session Chair: Lieven Eeckhout, Ghent University
Pynamic: The Python Dynamic Benchmark Behavior
G. L. Lee, D. H. Ahn, B. R. de Supinski, J. Gyllenhaal, P. Miller, Lawrence Livermore
National Laboratory
Delaunay Triangulation with Transactions and Barriers
M. L. Scott, M. F. Spear, L. Dalessandro, V. J. Marathe, University of Rochester
FacePerf: Benchmarks for Face Recognition Algorithms
D. S. Bolme, M. Strout, J. R. Beveridge, Colorado State University
HD-VideoBench: A Benchmark for Evaluating High Definition Digital Video
M. Alvarez, E. Salami, A. Ramirez, M. Valero, UPC and BSC
11:45 a.m. - 1:30 p.m. Lunch
1:30 p.m. - 3:00 p.m. Tracing and Online Characterization
Seekable Compressed Traces
Tip Moseley, Dirk Grunwald, University of Colorado at Boulder; Ramesh Peri, Intel
Analysis of Statistical Sampling in Microarchitecture Simulation: Metric, Methodology,
and Program Characterization
Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Wei-Chung Hsu, Pen-Chung Yew,
University of Minnesota
Efficient Disk I/O Characterization using Online Histograms in a Virtual Machine Hypervisor
Irfan Ahmad, VMware
3:00 p.m. - 3:30 p.m. Break
3:30 p.m. - 4:30 p.m. Data Center Applications
An Observation-Based Approach to Performance Characterization of Distributed n-Tier
Applications
Calton Pu, Akhil Sahai, HP Labs; Jason Parekh, Gueyoung Jung, Ji Bae, You-Kyung Cha,
Timothy Garcia, Danesh Irani, Jae Lee, Qifeng Lin, Georgia Institute of Technology
Workload Anaysis and Demand Prediction of Enterprise Data Center Applications
Daniel Gmach, Technische Universitat Munchen; Jerry Rolia, Ludmila Cherkasova, HP Labs;
Alfons Kemper, Technische Universitat Munchen
4:30 p.m. - 6:00 p.m.
Compact Workload Creation
SCRAP: A Statistical Approach for Creating Compact Representational Query Workload based
on Performance Bottlenecks
James A. Skarie, Biplob K. Debnath, David J. Lilja, Mohamed F. Mokbel,
University of Minnesota
Representative Multiprogram Workloads for Multithreaded Processor Simulation
Michael Van Biesbrouck, UCSD; Lieven Eeckhout, Ghent University;
Brad Calder, UCSD, Microsoft
Hierarchical Means: Single Number Benchmarking with Workload Cluster Analysis
Richard M. Yoo, Hsien-Hsin S. Lee, Georgia Tech.; Han Lee, Kingsum Chow, Intel
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