[Sigarch-members] SIGARCH-MSG: 2nd August 2007 Digest of SIGARCH Messages

["Doug Burger" <dburger@xxxxxxxxxxxxx>]

This is the 2nd August 2007 Digest of SIGARCH Messages (sigarch-aug07b):

* GPGPU 2007 Call for Papers: Workshop on General Purpose Processing Using GPUs
  http://www.ece.neu.edu/GPGPU/
  Submitted by Prof. David Kaeli <kaeli@xxxxxxxxxxx>

* IEEE Computer Architecture Letters: New Papers published on-line by IEEE Computer Architecture Letters
  http://www.comp-arch-letters.org
  Submitted by Kevin Skadron <skadron@xxxxxxxxxxxxxxx>


--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@xxxxxxx

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Doug Burger			  Office:	       3.432 ACES
Associate Professor		  Phone:	     512-471-9795
Department of Computer Sciences	  Assistant:	     512-232-7460
The University of Texas at Austin Fax:		     512-232-1413
1 University Station, #C0500	  E-mail:   dburger@xxxxxxxxxxxxx
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* GPGPU 2007 Call for Papers: Workshop on General Purpose Processing Using GPUs

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      CALL FOR PAPERS
******************************      

Workshop on General Purpose Processing Using GPUs
Northeastern University
Boston, MA USA     
October 4, 2007

Overview: The goal of this workshop is to provide a forum these 
general-purpose purpose programming environments and platforms, 
as well as discuss applications that have been able to harness 
the horsepower provided by these platforms.  This year's work is 
particularly interested in imaging applications.   Papers are being 
sought on many aspects of GPUs, including (but not limited to):

+ GPU applications              + GPU software and operating systems 
+ GPU programming environments  + GPU power/efficiency	 
+ GPU architectures             + GPU benchmarking/measurements

Paper Submission: Authors should submit a 8 page paper in 
IEEE double-column style to gpgpu@xxxxxxxxxxxx

Industry Participation: The workshop encourages participation by 
GPU manufacturers, software vendors, or companies which develop or market 
products used by the GPU community. Any company interested in participating 
in the workshop should contact the workshop organizer at gpgpu@xxxxxxxxxxxx

Important Dates:
Paper submission: August 28, 2007
Author notification: September 7, 2007
Final paper: September 14, 2007

Copies of final papers will be made available at the workshop. 
In addition, selected papers will be invited to be part of a special 
issue of an ACM or IEEE journal or magazine.
For more information, see the GPGPU 2007 web 
page: http://www.ece.neu.edu/GPGPU/

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New papers published online by IEEE Computer Architecture Letters


Computer Architecture Letters announces our three most recent papers,
which are available now via IEEE Xplore. We happy to report that, as recognition of 
Computer Architecture Letters has grown, the submission rate has nearly doubled this year.  
We continue to seek new submissions and remain committed to fast and accurate review.  Our 
mean time to decision in 2007 has been 24 days, with an acceptance rate of approximately 25%.
For more information on submission, please see http://www.comp-arch-letters.org


- J. Zebchuk and A. Moshovos.  "A Building Block for Coarse-Grain Optimizations in the 
On-Chip Memory Hierarchy."  Computer Architecture Letters, vol. 6, June 2007.


- A. Das, S. Ozdemir,  G. Memik, J. Zambreno, and A. Choudhary. "Microarchitectures for 
Managing Chip Revenues under Process Variations." Computer Architecture Letters, vol. 6, 
June 2007.


- J. Kim, J. Balfour, and W. Dally. "Flattened Butterfly Topology for On-Chip Networks." 
Computer Architecture Letters, vol. 6, July 2007.


Abstracts
---------
- J. Zebchuk and A. Moshovos.  "A Building Block for Coarse-Grain Optimizations in the 
On-Chip Memory Hierarchy."  Computer Architecture Letters, vol. 6, June 2007.


Abstract:
Current on-chip block-centric memory hierarchies exploitaccess patterns at the fine-grain 
scale of small blocks.Several recently proposed memory hierarchy enhancementsfor coherence 
traffic reduction and prefetching suggest thatadditional useful patterns emerge with a 
macroscopic,coarse-grain view. This paper presents RegionTracker, adual-grain, on-chip 
cache design that exposes coarse-grainbehavior while maintaining block-level communication.
RegionTracker eliminates the extraneous, often imprecisecoarse-grain tracking structures of 
previous proposals. Itcan be used as the building block for coarse-grainoptimizations, 
reducing their overall cost and easing theiradoption. Using full-system simulation of a 
quad-core chipmultiprocessor and commercial workloads, we demonstratethat RegionTracker 
overcomes the inefficiencies of previouscoarse-grain cache designs. We also demonstrate 
how RegionTracker boosts the benefits and reduces the cost of apreviously proposed snoop 
reduction technique.


- A. Das, S. Ozdemir,  G. Memik, J. Zambreno, and A. Choudhary. "Microarchitectures for 
Managing Chip Revenues under Process Variations." Computer Architecture Letters, vol. 6, 
June 2007.


Abstract:
As transistor feature sizes continue to shrink intothe sub-90nm range and beyond, the 
effects of process variationson critical path delay and chip yields have amplified. A 
commonconcept to remedy the effects of variation is speed-binning, bywhich chips from a 
single batch are rated by a discrete range offrequencies and sold at different prices. In 
this paper, we discussstrategies to modify the number of chips in different bins andhence 
enhance the profits obtained from them. Particularly, wepropose a scheme that introduces 
a small Substitute Cacheassociated with each cache way to replicate the data elementsthat 
will be stored in the high latency lines. Assuming a fixedpricing model, this method 
increases the revenue by as much as 13.8% without any impact on the performance of the chips.


- J. Kim, J. Balfour, and W. Dally. "Flattened Butterfly Topology for On-Chip Networks." 
Computer Architecture Letters, vol. 6, July 2007.


Abstract:
With the trend towards increasing number of cores in a multicore processors, the on-chip 
network that connects the cores needs to scale efficiently. In this work, we propose the 
use of high-radix networks in on-chip networks and describe how the flattened butterfly 
topology can be mapped to on-chip networks. By using high-radix routers to reduce the 
diameter of the network, the flattened butterfly offers lower latency and energy consumption
than conventional on-chip topologies. In addition, by properly using bypass channels in the 
flattened butterfly network, non-minimal routing can be employed without increasing latency 
or the energy consumption.