Re: [Gems-users] non-cacheable memory

[Dan Gibson <degibson@xxxxxxxx>]

SimicsProcessor.C:

It looks something like this:
 if (m_current_instruction_count != SIMICS_get_insn_count(m_proc)) {
   clearActiveRequestVector();
   m_current_instruction_count = SIMICS_get_insn_count(m_proc);
 }

Regards,
Dan

Dave Z. wrote:
> --- Mike Marty <mikem@xxxxxxxxxxx> wrote:
>
>   
> > > If you are not interested in modeling the memory
> > >       
> > system affects of issuing
> >     
> > > a request to memory, possibly incurring
> > >       
> > interconnect delays and etc., then
> >     
> > > sure, return a fixed number of stall cycles to
> > >       
> > Simics
> >     
> > This actually won't work.  You first need to stall
> > Simics, then after the
> > stall elapses, Simics will ask again if it can
> > proceed and you need to
> > then return a stall of 0.
> >
> >     
> Where does such an implementation take place in Ruby
> code (so that I can have an example to take a look)? 
>
> Thanks
>
> Dave
>
>
>  
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