Hi,
I want to simulate a multi core system in Opal which executes only the
User
instructions.
The m_fetch_at data is helpful in this measure. I have pasted the code
which i used in the fetchInstSimple() in pseq.C in Opal.
I check if the PC belongs to a supervisor instructions by this code.
pstate_s = m_fetch_at[proc]->pstate;
priv_s = ((pstate_s & 0x4) == 0x4);
if (priv_s){
fprintf (pctrace,"--------Processor : %d--------\n",m_id);
fprintf (pctrace,"SuperVisor Instructions fetchPhyPC : 0x%0llx\n
",fetchPhysicalPC);
//I advance simics
M_PSTATE->simcontinue( 1, proc );
//Am not sure abt this part. In order to prevent a squash due to
inconsistency, //I copy the simics register to Opal .
m_fetch_at[proc]->pc = M_PSTATE->getControl(CONTROL_PC, proc);
m_fetch_at[proc]->npc = M_PSTATE->getControl(CONTROL_NPC, proc);
m_fetch_at[proc]->tl = M_PSTATE->getControl(CONTROL_TL, proc);
m_fetch_at[proc]->pstate = M_PSTATE->getControl( CONTROL_PSTATE, proc );
m_fetch_at[proc]->cwp = M_PSTATE->getControl(CONTROL_CWP, proc);
m_fetch_at[proc]->gset = pstate_t::getGlobalSet( m_fetch_at[proc]->pstate
);
if ( ISADDRESS32(m_fetch_at[proc]->pstate) ) {
m_fetch_at[proc]->pc = AM64( m_fetch_at[proc]->pc );
m_fetch_at[proc]->npc = AM64( m_fetch_at[proc]->npc );
}
m_ooo.at[proc] = *(m_fetch_at[proc]);
m_inorder[proc].at[proc] = *(m_fetch_at[proc]);
}
else{
//It is a user instruction . I proceed normally.
}
The problem is that once the processor hits a Supervisor Instructions it
stalls at the same PC. It doesn't move on to the next instruction.It keeps
fetching the same Supervisor Intsruction.
What am I doing wrong?
Suhail
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