This is the 1st June 2007 Digest of SIGARCH Messages (sigarch-jun07a):
* ASPLOS 2008 Call For Papers: ASPLOS XIII (13th International Conference on Architectural Support for Programming Languages and Operating Systems)
http://research.microsoft.com/asplos08/
Submitted by Onur Mutlu <onur@xxxxxxxxxxxxx>
* WESS'2007 Call for Papers: 2nd Workshop on Embedded Systems Security (WESS'2007) - A Workshop of ACM EMSOFT'2007
http://netsys.ece.upatras.gr/emsoft07/
Submitted by Sri Parameswaran <sridevan@xxxxxxxxxxxxxxx>
* WIOSCA 2007 Call for Participation: Workshop on the Interaction between
Operating Systems and Computer Architecture
http://www.ideal.ece.ufl.edu/wiosca
Submitted by James M. Poe II <jpoe@xxxxxxx>
* New papers published online by Computer Architecture Letters
http://www.comp-arch-letters.org
Submitted by Kevin Skadron <skadron@xxxxxxxxxxxxxxx>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@xxxxxxx
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Doug Burger Office: 3.432 ACES
Associate Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
The University of Texas at Austin Fax: 512-232-1413
1 University Station, #C0500 E-mail: dburger@xxxxxxxxxxxxx
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* ASPLOS 2008 Call For Papers: ASPLOS XIII (13th International Conference on Architectural
Support for Programming Languages and Operating Systems), Seattle, WA
C A L L F O R P A P E R S
ASPLOS XIII (13th International Conference on Architectural Support for Programming Languages and Operating Systems), Seattle, WA
March 1 - 5, 2008
http://research.microsoft.com/asplos08/
Sponsors: SIGARCH, SIGPLAN, SIGOPS
ASPLOS is a multi-disciplinary conference for research that spans the boundaries of hardware,
computer architecture, compilers, languages, operating systems, networking, and applications.
ASPLOS provides a high quality forum for scientists and engineers to present their latest
research findings in these rapidly changing fields. It has captured some of the major
computer systems innovations of the past two decades (e.g., RISC and VLIW processors, small
and large-scale multiprocessors, clusters and networks-of-workstations, optimizing compilers,
RAID, and network-storage system designs).
This conference occurs at a time when computer architecture is facing great challenges, due
both to the end of single-processor performance scaling and to new demands imposed by mobile
and gigascale computing. Multi-disciplinary research is increasingly important as boundaries
between hardware/software and local/network computing blur, as the form and capabilities of
computing devices becomes ever more varied, and as users and applications continue to expand.
In addition to the main program, this upcoming ASPLOS will offer several tutorials and
workshops on a variety of focus areas.
Like its predecessors, the ASPLOS 2008 conference will focus on ground-breaking research,
articularly efforts focusing on the interplay of hardware and software systems. The program
committee welcomes research papers on a wide range of non-traditional topics that emphasize
the multi-disciplinary aspects of their work. Full papers are solicited on, but not limited
to, these topics:
- Interaction of operating systems, compilers, programming languages, and architectures
- Hardware/software issues for new platforms, from sensor networks to wireless PDAs to
wall-sized displays
- Hardware/software issues focusing on Internet services
- Hardware/software platforms for delivering graphics and multimedia
- Embedding computation and storage (e.g., caches) within networks
- Case studies of hardware/software design in novel experimental systems
- Studies of Internet applications and services with implications for systems design
- Security and availability issues for current/future computer systems
- Evaluations of experimental systems for performance, power, availability
- Effect of technology and application drivers on architectures, operating systems, or
compilers
***Important Dates and Deadlines***
Abstract Deadline: August 1, 2007 (11pm Pacific Daylight Savings Time)
Full Paper Deadline: August 7, 2007 (11pm Pacific Daylight Savings Time)
Rebuttal Period: October 11-12, 2007
Notification of Acceptance: November 1, 2007
Final Paper Submission: December 31, 2007
General Chair:
Susan Eggers, University of Washington
Program Chair:
James Larus, Microsoft Research
Steering Committee:
Jack Davidson, University of Virginia
Mark D. Hill, University of Wisconsin
Norm Jouppi, HP Labs
Margaret Martonosi, Princeton University
Keith Marzullo, UC San Diego
Kathryn McKinley, University of Texas
Program Committee:
Ali-Reza Adl-Tabatabai, Intel
Anastassia Ailamaki, CMU
Saman Amarasinghe, MIT
Krste Asanovic, MIT
Luiz Barroso, Google
Doug Burger, Univ. Texas
Brian Bershad, Univ. Washington
Ras Bodik, UC Berkeley
Pradip Bose, IBM
Richard Draves, Microsoft Research
Seth Goldstein, CMU
Richard Johnson, NVIDIA
Eddie Kohler, UCLA
Christos Kozyrakis, Stanford
Chandra Krintz, UC Santa Barbara
Eliot Moss, Univ. Massachusetts
Gilles Muller, Ecole des Mines
Li-Shiuan Peh, Princeton
Mendel Rosenblum, Stanford
Mike Smith, Harvard
Steve Swanson, UC San Diego
Willy Zwaenepoel, EPFL
Workshops and Tutorials: Mike Swift, University of Wisconsin, Madison
Wild and Crazy Ideas Session: Steve Swanson, UC San Diego
Publications: Diana Franklin, California Polytechnic State University
Publicity: Onur Mutlu, Microsoft Research
Finance Chair: Craig Zilles, University of Illinois, Urbana-Champaign
Local Arrangements: Mark Oskin, University of Washington
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* WESS'2007 Call for Papers: 2nd Workshop on Embedded Systems Security (WESS'2007)
A Workshop of ACM EMSOFT'2007
2nd Workshop on Embedded Systems Security
A Workshop of ACM EMSOFT'2007
October 4, 2007
Embedded computing systems are widely adopted in application areas ranging from safety-
critical systems to vital information management. The inherent characteristics of embedded
systems and the advent of Internet-enabled devices introduce a large number of security
issues. Embedded systems are vulnerable to remote intrusion, power and timing attacks,
hijacking, etc. These vulnerabilities are different from traditional workstation security
issues due to the physical properties, applications, and performance limitations of embedded
systems.This workshop provides a forum for researchers to present novel ideas on addressing
security issues that arise in embedded systems. Of particular interest are security topics
that are unique to embedded systems. Such topics include but are not limited to:
·Security architectures for embedded systems
·Security of Internet-enabled embedded systems
·Security planning and provisioning in embedded systems
·Power-related attacks and countermeasures
·Timing-related attacks and countermeasures
·Novel attacks and countermeasures
·Security of sensor networks
·Benchmarks for embedded system security
·Case studies
Accepted papers will be provided as proceedings to workshop participants. The best papers
will be selected for publication in a special issue of the Springer Journal of Design
Automation for Embedded Systems.
Important Dates:
Abstract registration: June 13, 2007
Full paper submission: June 20, 2007
Notification of results: July 30, 2007
Camera-ready copy due: August 20, 2007
ESWEEK: September 30 - October 5, 2007
Submission Instructions: Original papers should be no more than 6 pages in length on
8.5 x 11" paper with fonts of at least 10 point and should be submitted as PDF on EDAS.
Submitted papers need not conform to ACM typesetting guidelines, but authors of accepted
papers must submit final versions that adhere to the 2-column ACM format by the
camera-ready copy due date. The program chairs reserve the right to desk-reject papers
without further review if they are deemed to be outside the scope of this workshop.
Steering Committee:
Wayne Wolf Princeton University USA (Chair)
Catherine Gebotys University of Waterloo Canada
Dimitrios Serpanos University of Patras Greece
Program Committee:
Sri Parameswaran University of New South Wales Australia (Co-chair)
Tilman Wolf University of Massachusetts USA (Co-chair)
Yun Cheol Baek Princeton University USA
Young Ik Eom Sungkyunkwan University Korea
Jinwoo Kim John Jay College of Criminal Justice USA
Phil Koopman Carnegie Mellon University USA
David Lie University of Toronto Canada
David Naccache École Normale Supérieure France
Christof Paar Bochum University Germany
Reinhard Posch Graz University of Technology Austria
Srivaths Ravi NEC Laboratories Princeton USA
Sean Smith Dartmouth College USA
Ingrid Verbauwhede K.U. Leuven Belgium
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* WIOSCA 2007 Call for Participation: Workshop on the Interaction between
Operating Systems and Computer Architecture
~ Call for Participation ~
Workshop on the Interaction between
Operating Systems and Computer Architecture
( WIOSCA 2007)
http://www.ideal.ece.ufl.edu/wiosca
Held in Conjunction with the
34th Annual International Symposium on Computer Architecture
Part of the 2007 Federated Computer Research Conference
( ISCA - 34 )
Please join us on Sunday, June 10th, 2007 for the Third Annual Workshop
on the Interaction between Operating Systems and Computer Architecture.
WIOSCA seeks to provide a forum for researchers, engineers, and students
from both academia and industry to discuss their latest research on
characterizing, modeling, and optimizing the interaction between operating
systems and hardware - in light of emerging architecture paradigms and
computing technology. This year's workshop features two distinguished
keynote speakers, five technical papers, and a panel discussion. Please
visit our website for a more detailed program. We look forward to meeting
you in San Diego.
Program
~~~~~~~
Keynote I: Burton Smith, Microsoft Technical Fellow
Keynote II: Beng-Hong Lim, VMWare Senior Director of R&D,
"Virtualizing Beyond the Box: Architectural Support for
a Distributed, Virtualized Compute Fabric"
Session 1:
* Desktop Workload Characterization for CMP/SMT and Implications for
Operating System Design, Sven Bachthaler, Fernando Belli, Alexandra
Fedorova (Simon Fraser University)
* The Cost of IPC: an Architectural Analysis, Isaac Gelado, Javier Cabezas,
Lluis Vilanova, Nacho Navarro (Universitat Politecnica de Catalunya)
* Re-architecting VMMs for Multicore Systems: The Sidecore Approach,
Sanjay Kumar, Himanshu Raj, Karsten Schwan, Ivan Ganev
(Georgia Institute of Technology)
Session 2:
* Managing Shared L2 Caches on Multicore Systems in Software, David Tam,
Reza Azimi, Livio Soares, Michael Stumm (University of Toronto)
* Base Vectors: A Potential Technique for Microarchitectural
Classification of Applications, Dan Doucette, Alexandra Fedorova
(Simon Fraser University)
Panel: Challenges and Opportunities for System Software (OS/VM)
in the Multi-core Era
* Moderator: Emmett Witchel (UT-Austin)
* Panelist:
Konrad Lai (Intel)
Beng-Hong Lim (VMware)
Chuck Moore (AMD)
Burton Smith (Microsoft)
James Smith (Wisconsin)
Michael Swift (Wisconsin)
Yuanyuan Zhou (UIUC)
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* New papers published online by Computer Architecture Letters
Computer Architecture Letters announces our four most recent papers. We continue to seek new submissions and remain committed to fast and accurate review. Our mean time to decision in 2007 has been 23 days, and our acceptance rate is currently about 23%. For more information on submission, please see http://www.comp-arch-letters.org
- Yoav Etsion and Dror G. Feitelson, "Probabilistic Prediction of Temporal Locality," IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007.
- Z. Guz, I. Keidar, A. Kolodny, and U. Weiser. "Nahalal: Cache Organization for Chip Multiprocessors," IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007.
- J. Joao, O. Mutlu, H. Kim, and Y. Patt. "Dynamic Predication of Indirect Jumps," IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007.
Abstracts
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- Yoav Etsion and Dror G. Feitelson, "Probabilistic Prediction of Temporal Locality," IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007.
Abstract:
The increasing gap between processor and memory speeds, as well as the introduction of multi-core CPUs, have exacerbated the dependency of CPU performance on the memory subsystem. This trend motivates the search for more efficient caching mechanisms, enabling both faster service of frequently used blocks and decreased power consumption. In this paper we describe a novel, random sampling based predictor that can distinguish transient cache insertions from non-transient ones. We show that this predictor can identify a small set of data cache resident blocks that service most of the memory references, thus serving as a building block for new cache designs and block replacement policies. Although we only discuss the L1 data cache, we have found this predictor to be efficient also when handling L1 instruction caches and shared L2 caches.
- Z. Guz, I. Keidar, A. Kolodny, and U. Weiser. "Nahalal: Cache Organization for Chip Multiprocessors," IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007.
Abstract:
This paper addresses cache organization in Chip Multiprocessors (CMPs). We show that in CMP systems it is valuable to distinguish between shared data, which is accessed by multiple cores, and private data accessed by a single core. We introduce Nahalal, an architecture whose novel floorplan topology partitions cached data according to its usage (shared versus private data), and thus enables fast access to shared data for all processors while preserving the vicinity of private data to each processor. Nahalal exhibits significant improvements in cache access latency compared to a traditional cache design.
- J. Joao, O. Mutlu, H. Kim, and Y. Patt. "Dynamic Predication of Indirect Jumps," IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007.
Abstract:
Indirect jumps are used to implement increasingly common programming language constructs such as virtual function calls, switch-case statements, jump tables, and interface calls. Unfortunately, the prediction accuracy of indirect jumps has remained low because many indirect jumps have multiple targets that are difficult to predict even with specialized hardware.
This paper proposes a new way of handling hard-to-predict indirect jumps: dynamically predicating them. The compiler identifies indirect jumps that are suitable for predication along with their control-flow merge (CFM) points. The microarchitecture predicates the instructions between different targets of the jump and its CFM point if the jump turns out to be hard-to-predict at run time. We describe the new indirect jump predication architecture, provide code examples showing why it could reduce the performance impact of jumps, derive an analytical cost-benefit model for deciding which jumps and targets to predicate, and present preliminary evaluation results.
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