Re: [Gems-users] FILE_SPECIFIED Question?

[Niket <niketa@xxxxxxxxxxxxx>]

The configuration you have created is a 8 processor system with 2 L2 
banks and 2 Routers connecting various components. It does not 
necessarily imply a 2-chip configuration. For instance, all these 
connections are also valid for a single chip system. The 
NUM_PROCS_PER_CHIP controls that. You might also want to use the 
appropriate protocol for that.
If you want to use a 2-chip configuration with 4 procs/chip, I believe 
you can use the MSI_MOSI_CMP_directory protocol. However, the L2's would 
not be unified between the 2-chips. The 2-chips in that case would be 
connected by the link between Routers 0 and 1.
I am not sure whether there is a protocol with the GEMS distribution 
that lets you use a unified L2 across 2 chips. The GEMS team might 
clarify that.
Cheers,
Niket

hb166307@xxxxxxxx wrote:
> Gems Users,
>
> Could anyone provide me with some clarification? I created this file and was
> trying to make sure my interpretation is correct. I believe the network
> described below is an eight processors system organized as 2 chips with 4
> processors per chip with 4 private L1 Cache's and a unified L2 cache. I am
> assuming the two chips are connected by their L2's. 
>
> ext_node:L1Cache:0 int_node:0 link_latency:1 
> ext_node:L1Cache:1 int_node:0 link_latency:1 
> ext_node:L1Cache:2 int_node:0 link_latency:1 
> ext_node:L1Cache:3 int_node:0 link_latency:1 
> ext_node:L2Cache:0 int_node:0 link_latency:1 
>
> ext_node:L1Cache:4 int_node:1 link_latency:1 
> ext_node:L1Cache:5 int_node:1 link_latency:1 
> ext_node:L1Cache:6 int_node:1 link_latency:1 
> ext_node:L1Cache:7 int_node:1 link_latency:1 
> ext_node:L2Cache:1 int_node:1 link_latency:1
> int_node:0 int_node:1 link_latency:1 bw_multiplier:16
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